专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10839901B1 Electronic device and operating method of electronic device 有权
公开(公告)号：US10839901B1
公开(公告)日：2020-11-17
申请号：US16661551
申请日：2019-10-23
申请人： SK hynix Inc.
发明人： Hyung Dong Lee , Tae Hoon Kim
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0026 , G11C13/0028 , G11C2013/005 , G11C2013/0054 , G11C2213/15 , G11C2213/72
摘要： A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.

2. 发明授权

US10614880B2 Memory system for controlling read voltage using cached data and operation method of the same 有权
公开(公告)号：US10614880B2
公开(公告)日：2020-04-07
申请号：US15831979
申请日：2017-12-05
申请人： SK hynix Inc.
发明人： Sang-Gu Jo , Jung-Hyun Kwon , Sung-Eun Lee , Yong-Ju Kim
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26 , G11C16/34 , G06F3/06 , G11C7/22 , G06F13/16 , G11C13/00
CPC分类号： G11C11/5642 , G06F3/0679 , G06F13/1626 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C2013/005 , G11C2207/2245 , G11C2207/2254
摘要： A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

3. 发明申请

US20180277204A1 MEMORY SYSTEM 审中-公开
公开(公告)号：US20180277204A1
公开(公告)日：2018-09-27
申请号：US15703070
申请日：2017-09-13
申请人： Toshiba Memory Corporation
发明人： Marie TAKADA , Masanobu SHIRAKAWA , Hiroshi YAO
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/1006 , G11C13/0026 , G11C13/0033 , G11C13/0069 , G11C2013/0042 , G11C2013/005 , G11C2013/0054 , G11C2013/0057 , G11C2213/71 , G11C2213/78 , G11C2213/79
摘要： A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. The first voltage is different from the second voltage. The first read data has a first value or a second value with the first value being different from the second value. The second read data has the first value or the second value.

4. 发明授权

US10083746B2 Memory device and method for operating memory device 有权
公开(公告)号：US10083746B2
公开(公告)日：2018-09-25
申请号：US15683876
申请日：2017-08-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Mu Hui Park
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2013/005 , G11C2013/0052 , G11C2013/0054 , G11C2213/72 , G11C2213/76
摘要： A memory device and a method for operating the memory device are provided. A resistive memory cell connected to a first node and configured to include a variable resistive element and an access element for controlling a current flowing through the variable resistive element. A detection circuit detects a threshold voltage of the access element and provides a detection current to a sensing node. A clamping circuit connected between the first node and the sensing node receives a first read voltage and ramps up a voltage of the first node. The first node is discharged by a discharge circuit when the detection current becomes equal to a bit line current flowing through the first node while the clamping circuit ramps up the voltage of the first node. A sense amplifier transitions an output voltage value when a voltage level of the sensing node becomes lower than a reference voltage.

5. 发明授权

US09842639B1 Systems and methods for managing read voltages in a cross-point memory array 有权
公开(公告)号：US09842639B1
公开(公告)日：2017-12-12
申请号：US15288874
申请日：2016-10-07
申请人： Kilopass Technology, Inc.
发明人： Frank Guo , Bruce Bateman
IPC分类号： G11C11/39
CPC分类号： G11C11/39 , G11C13/0033 , G11C2013/005
摘要： Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.

6. 发明申请

US20170352415A1 METHODS FOR DETERMINING THE RESISTIVE STATES OF RESISTIVE CHANGE ELEMENTS 有权
公开(公告)号：US20170352415A1
公开(公告)日：2017-12-07
申请号：US15175234
申请日：2016-06-07
申请人： Nantero Inc.
发明人： Qawi HARVARD
IPC分类号： G11C13/00 , H01L51/05
CPC分类号： G11C13/0023 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2213/77 , G11C2213/79 , G11C2213/82 , H01L51/0048 , H01L51/0558
摘要： Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.

7. 发明授权

US09564214B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09564214B2
公开(公告)日：2017-02-07
申请号：US14817392
申请日：2015-08-04
申请人： Kabushiki Kaisha Toshiba
发明人： Kazuhiko Yamamoto , Kunifumi Suzuki
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/33 , G11C2213/35 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/1608
摘要： According to one embodiment, a memory device includes a controller; a first electrode and a second electrode connected to the controller; and a variable resistance layer provided between the first electrode and the second electrode. The variable resistance layer has a first structure, and a second structure. The controller configured to be able to perform a first operation of applying a first voltage between the first electrode and the second electrode, a second operation of applying a second voltage between the first electrode and the second electrode and determining whether or not the variable resistance layer has the second structure, and a third operation of applying a third voltage between the first electrode and the second electrode having the interposed variable resistance layer determined to not have the second structure in the second operation.
摘要翻译：根据一个实施例，存储器件包括控制器; 连接到所述控制器的第一电极和第二电极; 以及设置在第一电极和第二电极之间的可变电阻层。可变电阻层具有第一结构和第二结构。控制器被配置为能够执行在第一电极和第二电极之间施加第一电压的第一操作，第二操作在第一电极和第二电极之间施加第二电压，并且确定可变电阻层具有第二结构，以及在具有在第二操作中被确定为不具有第二结构的插入的可变电阻层的第一电极和第二电极之间施加第三电压的第三操作。

8. 发明授权

US09484090B2 Read and write methods for a resistance change non-volatile memory device 有权
标题翻译：电阻变化非易失性存储器件的读写方法
公开(公告)号：US09484090B2
公开(公告)日：2016-11-01
申请号：US14635297
申请日：2015-03-02
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Yuhei Yoshimoto , Kazuhiko Shimakawa , Ken Kawai , Ryotaro Azuma
IPC分类号： G11C13/00 , G11C29/02 , G11C29/00 , H01L27/24 , H01L45/00 , G11C7/06
CPC分类号： G11C13/004 , G11C7/062 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/70 , G11C2013/005 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.
摘要翻译：提供从存储单元阵列选择存储单元的选择电路和用于读取所选存储单元中的电阻变化元件的电阻状态的读取电路。在构成多层存储单元阵列的奇数层和偶数层存储单元阵列的存储单元中，任何层中的每个存储单元都具有选择元件，第一电极，第一电阻改变层，第二电阻变化层和第二电极。所选择的存储单元是否位于多层存储单元阵列的任何层中，读取电路向所选存储单元施加电压以执行读取操作。施加到所选择的存储单元的电压使得第二电极参照所选择的存储单元中的第一电极变为正。

9. 发明授权

US09368553B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09368553B2
公开(公告)日：2016-06-14
申请号：US14624920
申请日：2015-02-18
申请人： Kabushiki Kaisha Toshiba
发明人： Yoshiaki Asao
IPC分类号： H01L27/24 , G11C13/00 , H01L23/528 , H01L45/00
CPC分类号： H01L27/2463 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0071 , H01L23/528 , H01L27/2436 , H01L45/065 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
摘要翻译：根据一个实施例，存储器件包括形成在衬底上的第一有源区，其在第三方向上延伸。存储器件还包括设置在第一有源区上的三个栅电极，其在与第三方向相交的第二方向上延伸。存储器件还包括至少两个或多个上层互连和至少两个或更多个下层互连，所述至少两个或更多个下层互连设置在第一有源区上，其沿与第二方向和第三方向相交的第一方向延伸。存储器件还包括三个第一晶体管，它们中的每一个设置在第一有源区和三个栅电极之间的交点处。存储器件还包括三个的第一晶体管是一个器件隔离晶体管和两个单元晶体管。

10. 发明授权

US08780611B2 Determining cell-state in phase-change memory 有权
标题翻译：确定相变存储器中的单元状态
公开(公告)号：US08780611B2
公开(公告)日：2014-07-15
申请号：US13573000
申请日：2012-08-13
申请人： Urs Frey , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sebastian
发明人： Urs Frey , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sebastian
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2013/005
摘要： A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (Vread); making a measurement (TM) that satisfies a predetermined condition where the predetermined condition depends on a cell current when the read voltage is applied; and determining a state of the cell based on the measurement.
摘要翻译：一种用于确定相变存储单元的状态的方法，装置和装置。该方法包括以下步骤：利用时变读取电压（Vread）偏置单元; 进行满足预定条件的预定条件的测量（TM），其中所述预定条件在施加所述读取电压时取决于单元电流; 以及基于所述测量来确定所述单元的状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式