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11. 发明授权

US06734741B2 Frequency synthesizer with digitally-controlled oscillator 有权
公开(公告)号：US06734741B2
公开(公告)日：2004-05-11
申请号：US10006607
申请日：2001-11-30
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

12. 发明授权

US08027657B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US08027657B2
公开(公告)日：2011-09-27
申请号：US10121761
申请日：2002-04-12
申请人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26 , H04L27/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

13. 发明授权

US07623838B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US07623838B2
公开(公告)日：2009-11-24
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

14. 发明授权

US07411444B2 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US07411444B2
公开(公告)日：2008-08-12
申请号：US10712593
申请日：2003-11-13
申请人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

15. 发明授权

US07356069B2 Spread spectrum demodulation using a subsampling communication receiver architecture 有权
标题翻译：使用子采样通信接收机架构进行扩频解调
公开(公告)号：US07356069B2
公开(公告)日：2008-04-08
申请号：US10132624
申请日：2002-04-25
申请人： Khurram Muhammad , Carl M. Panasik , Dirk Leipold
发明人： Khurram Muhammad , Carl M. Panasik , Dirk Leipold
IPC分类号： H04B1/707
CPC分类号： H03H15/00 , H03H19/004 , H04B1/0003 , H04B1/0025 , H04B1/28 , H04L27/24
摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional cycles of the first voltage waveform are obtained. The samples are obtained in response to a control signal indicative of a code used to produce the first voltage waveform, and the samples are combined to produce the second voltage waveform.
摘要翻译：第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。响应于指示用于产生第一电压波形的代码的控制信号而获得样本，并且采样被组合以产生第二电压波形。

16. 发明授权

US07057540B2 Sigma-delta (ΣΔ) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer 有权
标题翻译：结合直接采样混频器的Sigma-delta（SigmaDelta）模数转换器（ADC）结构
公开(公告)号：US07057540B2
公开(公告)日：2006-06-06
申请号：US10273217
申请日：2002-10-17
申请人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Feng Chen , Dirk Leipold
IPC分类号： H03M3/00
CPC分类号： H03M3/47 , H03M3/496 , H04B1/1036
摘要： A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.
摘要翻译： Σ-Δ模数转换器 - 具有噪声整形和高频操作等优点。然而，需要提供具有低噪声特性的高度过采样离散时间采样流所需的采样电路难以设计和实现。本发明提供了具有这种采样电路310的Σ-Δ混合器300。本发明公开了一种使用具有低噪声特性的开关电容器307,308和309的采样电路，同时能够提供高度过采样的离散时间采样流。

17. 发明授权

US07006813B2 Efficient charge transfer using a switched capacitor resistor 有权
公开(公告)号：US07006813B2
公开(公告)日：2006-02-28
申请号：US10147784
申请日：2002-05-16
申请人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of the rotating capacitors 1111 and 1112 is power inefficient. A power efficient and low-noise precharging operation is realized through the sharing of the charge on a feedback capacitor 1075 and 1080 that is significantly larger than the rotating capacitors 1111. Once a precharging operation is complete, the charge on the feedback capacitor 1075 and 1080 is refreshed from its residual charge level (rather than zero charge level) to a desired charge level.

18. 发明申请

US20050186920A1 Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor 审中-公开
标题翻译：噪声抑制和抖动的装置和方法，以提高数字RF处理器中的分辨率质量
公开(公告)号：US20050186920A1
公开(公告)日：2005-08-25
申请号：US11062254
申请日：2005-02-18
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
IPC分类号： H03C3/00 , H03L7/16 , H04B1/04 , H04B1/06 , H04B1/68
CPC分类号： H03L7/16 , H03L2207/50
摘要： A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.
摘要翻译：一种用于数字RF处理器（DRP）中的噪声和伪噪声抑制的新型装置和方法。本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。噪声抑制方案消除了通过电磁，电源，接地和基板路径传输的各种片上干扰源引起的噪声。噪声抑制方案允许所有数字PLL（ADPLL）以这样的方式操作，以避免产生通常由芯片上的干扰源的注入拉动效应产生的杂散。频率参考时钟重新定时与RF振荡器时钟同步，用于驱动DRP的整个数字逻辑电路。这确保了整个系统中不同的时钟沿不会出现相互漂移。还提出了一种提高ADPLL内数字转换器的分辨率质量的方法。该方法通过将参考时钟传递通过由Σ-Δ调制器控制的延迟电路来抖动参考时钟。由于TDC定时估计的不正确的量化，抖动参考时钟降低了对ADPLL输出的相位噪声的影响。

19. 发明授权

US08542616B2 Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing 有权
标题翻译：使用频率复用和共享处理的同时多信号接收和传输
公开(公告)号：US08542616B2
公开(公告)日：2013-09-24
申请号：US12250646
申请日：2008-10-14
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04L5/14
CPC分类号： H04B1/0075 , H03D7/1441 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03D2200/0047 , H03D2200/0074 , H03D2200/0084 , H03D2200/0088 , H04L5/06 , H04L5/143 , H04L27/3863 , H04L2027/0016
摘要： A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase/frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.
摘要翻译：一种使用频率复用和共享处理同时进行多信号接收和传输的新颖机制。可以使用一个或多个共享处理块来接收可能具有各种无线标准的多个RF信号，从而显着减少芯片空间和功率需求。共享组件包括本地振荡器，模数转换器，数字RX处理和数字基带处理。在操作中，针对每个期望的无线信号的多个RX前端电路产生频率多路复用并组合以产生单个组合IF信号的多个IF信号。组合的IF信号由共享处理块处理。对每个接收信号执行数字基带处理，以产生相应的数据输出。此外，使用单个本地振荡器执行同时的全双工发送和接收。在TX中使用的频率合成器的相位/频率调制从本地振荡器信号中去除，以在接收机中使用。

20. 发明授权

US08306176B2 Fine-grained gear-shifting of a digital phase-locked loop (PLL) 有权
标题翻译：数字锁相环（PLL）的细粒度换档
公开(公告)号：US08306176B2
公开(公告)日：2012-11-06
申请号：US10464982
申请日：2003-06-19
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03D3/24
CPC分类号： H03L7/107 , H03L7/087 , H03L7/093 , H03L2207/50
摘要： System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.
摘要翻译：通过对环路增益进行细微调整来提高数字PLL性能的系统和方法。优选实施例包括可逐渐调节环路增益的多个环路增益调节器（例如环路增益调节器605,606,607和608）。递增调节的环路增益被顺序地串联在一起，使得数字PLL的环路增益缓慢降低。通过缓慢地减小环路增益，数字PLL不受较小的噪声瞬变扰动，这将需要一些时间来解决。因此，数字PLL可以快速获取信号，然后在仅需要跟踪信号时减小其环路增益，从而降低其带宽。降低的带宽也降低了由于参考噪声贡献而导致的数字PLL中的整体噪声。

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