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1. 发明授权

US08321489B2 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US08321489B2
公开(公告)日：2012-11-27
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F17/10
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

2. 发明申请

US20110261871A1 ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION 有权
标题翻译：全数字频率合成与DCO增益计算
公开(公告)号：US20110261871A1
公开(公告)日：2011-10-27
申请号：US13175594
申请日：2011-07-01
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04B17/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

3. 发明授权

US08027657B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US08027657B2
公开(公告)日：2011-09-27
申请号：US10121761
申请日：2002-04-12
申请人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26 , H04L27/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

4. 发明授权

US08000428B2 All-digital frequency synthesis with DCO gain calculation 有权
标题翻译：全数字频率合成采用DCO增益计算
公开(公告)号：US08000428B2
公开(公告)日：2011-08-16
申请号：US10302029
申请日：2002-11-22
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

5. 发明授权

US07813462B2 Method of defining semiconductor fabrication process utilizing transistor inverter delay period 有权
标题翻译：利用晶体管反相器延迟周期定义半导体制造工艺的方法
公开(公告)号：US07813462B2
公开(公告)日：2010-10-12
申请号：US11550878
申请日：2006-10-19
申请人： Elida Isabel de Obaldia , Robert B. Staszewski , Dirk Leipold
发明人： Elida Isabel de Obaldia , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D3/24
CPC分类号： H04L27/361 , H03L7/091 , H03L7/0991 , H03L7/1806
摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
摘要翻译：一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。逆时间的计算提供了每个模具中制造工艺变化的直接相关性。

6. 发明授权

US07778610B2 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation with jitter estimation and correction 有权
标题翻译：振荡器和RF频率之间具有非谐波比的本地振荡器，使用具有抖动估计和校正的异或运算
公开(公告)号：US07778610B2
公开(公告)日：2010-08-17
申请号：US11844425
申请日：2007-08-24
申请人： Robert B. Staszewski , Nir Tal
发明人： Robert B. Staszewski , Nir Tal
IPC分类号： H04B1/40
CPC分类号： H03B21/00
摘要： A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.
摘要翻译：本地振荡器（LO）生成的新颖有用的装置和方法，其本地振荡器和RF频率之间具有非整数倍乘比。所呈现的LO产生方案可用于以指定频率产生I和Q方波，同时避免众所周知的谐波拉动问题。避免使用现有技术的模拟混频器，并用配置成产生正确的平均频率的XOR门代替。根据受控振荡器的分频时钟的状态，边沿被动态调整±T / 12或零。

7. 发明授权

US07756487B2 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using pulse generation and selection 有权
标题翻译：使用脉冲发生和选择，振荡器和RF频率之间具有非谐波比的本地振荡器
公开(公告)号：US07756487B2
公开(公告)日：2010-07-13
申请号：US11844453
申请日：2007-08-24
申请人： Gregory Lerner , Nir Tal , Robert B. Staszewski
发明人： Gregory Lerner , Nir Tal , Robert B. Staszewski
IPC分类号： H04B1/40
CPC分类号： H03B21/02 , H03K5/00006 , H03K5/13 , H03K5/1565
摘要： A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.
摘要翻译：本地振荡器（LO）生成的新颖有用的装置和方法，其本地振荡器和RF频率之间具有非整数倍乘比。所呈现的LO产生方案可用于以指定频率产生I和Q方波，同时避免众所周知的谐波拉动问题。输入信号被馈送到合成器，其被定时到RF频率L / N fRF的有理乘数。所生成的时钟信号除以因子Q，以L（N * Q）fRF的频率形成时钟的2Q相位，其中每相经过除法L.相位信号被输入到输出多个的脉冲。脉冲被输入到选择器，其选择在任何时间点输出哪个信号。通过控制选择器，输出时钟作为基于TDM的信号产生。任何杂项都可以通过可选过滤器去除。

8. 发明授权

US07692504B2 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US07692504B2
公开(公告)日：2010-04-06
申请号：US12030123
申请日：2008-02-12
申请人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
IPC分类号： H03B5/18
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：用于提供谐振信号的n阶振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括第n级复数LC容器的反馈回路，并被配置为产生谐振信号通过将中间信号的复数滤波形式反馈到放大器。

9. 发明授权

US07667511B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

10. 发明申请

US20080309524A1 Second-Order Polynomial, Interpolation-Based, Sampling Rate Converter and Method and Transmitters Employing the Same 审中-公开
标题翻译：二阶多项式，基于插值的采样率转换器及其使用的方法和发送器
公开(公告)号：US20080309524A1
公开(公告)日：2008-12-18
申请号：US12121090
申请日：2008-05-15
申请人： Ioannis L. Syllaios , Khurram Waheed , Robert B. Staszewski
发明人： Ioannis L. Syllaios , Khurram Waheed , Robert B. Staszewski
IPC分类号： H03M7/00
CPC分类号： H03H17/0685 , H03H17/028
摘要： A sampling rate converter, a method of performing digital sampling rate conversion and a wireless transmitter incorporating the filter or the method. In one embodiment, the sampling rate converter includes: (1) an input configured to receive digital data from a first clock domain sampled at a first sampling rate, (2) an output configured to provide digital data to a second clock domain sampled at a second sampling rate that differs from the first sampling rate and (3) a filter with a second-order, polynomial-based impulse response coupled to the input and the output and configured to apply coefficients having only one nonunitary divisor to the digital data from the first clock domain.
摘要翻译：采样率转换器，执行数字采样率转换的方法和包含滤波器或方法的无线发射器。在一个实施例中，采样率转换器包括：（1）被配置为从以第一采样率采样的第一时钟域接收数字数据的输入，（2）被配置为将数字数据提供给在第二采样率与第一采样率不同，以及（3）具有耦合到输入和输出的二阶多项式的脉冲响应的滤波器，并且被配置为将仅具有一个非维数除数的系数应用于来自第一个时钟域

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