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    • 13. 发明授权
    • Sub-calibre projectile of the fin-stabilised type incorporating a sabot and a penetrator
    • 翅片稳定型的子口径射弹,包括一个破坏物和一个穿透器
    • US08316773B2
    • 2012-11-27
    • US12805170
    • 2010-07-15
    • Nicolas EchesArnaud GuillouxRichard Roy
    • Nicolas EchesArnaud GuillouxRichard Roy
    • F42B14/06
    • F42B14/062
    • A sub-caliber projectile of the fin-stabilized type incorporating a sabot and a penetrator linked together by shape matching linking means, said linking means incorporating a first profile machined at a bore of said sabot and cooperating with a second profile on said penetrator, each of said first and second profiles having a shape according to a section in an axial plane that alternates teeth and grooves, the axial play between one of said teeth of said penetrator and one of said grooves forming the housing of said one of said teeth in said sabot being variable along the axis of said projectile, wherein said linking means incorporate a front part (F) and a rear part (R) in which the play, at a mean temperature, between said penetrator teeth and the housings of said teeth in said sabot is variable, the play, firstly, increasing between said median zone (M) of said sabot and a front end of said sabot and, secondly, increasing between said median zone (M) of said sabot and a rear end of said sabot.
    • 一种具有通过形状匹配连接装置连接在一起的鞋底和穿透器的翅片稳定型的子口径射弹,所述连接装置包括在所述刺刀的孔处加工并与所述穿透器上的第二轮廓配合的第一轮廓, 所述第一和第二轮廓具有根据在轴向平面中切换齿和凹槽的截面的形状,所述穿透器的所述齿之一和所述凹槽中的一个之间的轴向游隙形成所述齿的所述齿的所述一个的壳体 所述突起沿所述抛射体的轴线是可变的,其中所述连接装置包括前部(F)和后部(R),其中平均温度下所述穿透齿与所述牙齿的壳体在所述 破坏是可变的,游戏中,首先,在所述破坏物的所述中间区域(M)和所述破坏物的前端之间增加,其次,在所述破坏物的所述中间区域(M)和 说屁股
    • 14. 发明授权
    • State maintenance pulsing for a memory device
    • 用于存储设备的状态维护脉冲
    • US07379381B1
    • 2008-05-27
    • US11175057
    • 2005-07-05
    • Richard RoyFarid Nemati
    • Richard RoyFarid Nemati
    • G11C8/00
    • G11C11/404G11C11/406G11C11/40622
    • State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.
    • 描述了存储器单元的状态维护,更具体地,描述了比其他存储器单元更频繁地状态维持所标识的存储器单元的脉冲。 存储器阵列包括存储器单元阵列。 状态维护电路耦合到存储器单元阵列。 状态维护电路被配置为在第一恢复地址和第二恢复地址之间进行选择。 在给定的操作周期中,第一恢复地址与存储器单元阵列中的第一行相关联,并且第二恢复地址与存储器单元阵列中的第二行相关联。 第一行具有耦合到其上的第一存储单元。 第二行具有与其耦合的第二存储单元。 第一存储器单元能够以第一恢复循环频率通过阈值保持时间。 第二存储器单元能够以第二恢复循环频率通过阈值保持时间。 恢复循环的第二个频率大于恢复循环的第一个频率。
    • 15. 发明授权
    • Bitline shielding for thyristor-based memory
    • 基于晶闸管的存储器的位线屏蔽
    • US07319622B1
    • 2008-01-15
    • US11174813
    • 2005-07-05
    • Richard Roy
    • Richard Roy
    • G11C7/00
    • G11C7/02G11C5/025G11C7/12G11C7/18G11C2211/5614
    • Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.
    • 用于向存储器单元写入和读取信息的方法和装置。 对于读取,写入路径用于将电子屏蔽来自与要读取的存储器单元相关联的位线的至少一个相邻位线,并且读取存储器单元,同时将至少一个相邻位线与与...相关联的位线电屏蔽 正在读取存储单元。 对于写入,写入路径用于在与要写入的存储器单元相关联的位线的至少一个相邻位线处电屏蔽; 耦合到字线的存储单元被读取和缓冲; 并且所述存储单元被写入,而所述至少一个相邻位线与所述存储单元的写入电屏蔽。
    • 17. 发明授权
    • Centrally decoded divided wordline (DWL) memory architecture
    • 集中解码分割字线(DWL)内存架构
    • US06236618B1
    • 2001-05-22
    • US09542033
    • 2000-04-03
    • Richard Roy
    • Richard Roy
    • G11C800
    • G11C8/14
    • A divided wordline memory architecture for memory compilers wherein a main memory array is organized into a plurality of local memory arrays. A plurality of local wordline decoders are provided such that each local memory array is associated with a local wordline decoder for selecting local wordline segments. Main wordline signals are generated based on a first portion of wordline address signals in a main wordline decoder provided as an integrated centrally located decoder structure. A combination of Plane signals, Set signals, or both, which are generated in the integrated centrally located decoder structure, are provided to the local wordline decoder in conjunction with a portion of the main wordline signals for selecting a local wordline segment based on a select main wordline signal and one of a select Plane signal, a select Set signal, or a combination of both.
    • 一种用于存储器编译器的分割字线存储器架构,其中主存储器阵列被组织成多个本地存储器阵列。 提供多个本地字线解码器,使得每个本地存储器阵列与用于选择本地字线段的本地字线解码器相关联。 主字线信号基于作为集成的中央定位的解码器结构提供的主字线解码器中的字线地址信号的第一部分生成。 在集成的位于中心的解码器结构中生成的平面信号,设置信号或两者的组合,与主字线信号的一部分相结合地提供给本地字线解码器,用于基于选择来选择本地字线段 主字线信号和选择平面信号之一,选择设置信号或两者的组合。