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    • 16. 发明授权
    • PSRR in a voltage reference circuit
    • 电压参考电路中的PSRR
    • US08493137B2
    • 2013-07-23
    • US13234766
    • 2011-09-16
    • Marco PasseriniFrancesco ManninoChiara Missiroli
    • Marco PasseriniFrancesco ManninoChiara Missiroli
    • G05F1/575H02M3/16
    • H03M1/0845H03M1/765
    • Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.
    • 用于参考电压架构的器件和电路,可通过改善输出晶体管的饱和裕度来增加PSRR参数。 例如,器件可以包括耦合在第一电源线和电路节点之间的电流源,耦合在电路节点和第二电源线之间的电压产生电路,以分别在其电压节点处产生多个电压, 耦合到电压产生电路和输出节点的电压节点并且被配置为选择并输出电压到输出节点的多路复用器,以及被配置为将电压中的一个电压提供给电路节点的控制电路。
    • 20. 发明授权
    • Droop reduction circuit for charge pump buck converter
    • 电荷泵降压转换器的下降电路
    • US09413232B2
    • 2016-08-09
    • US14734720
    • 2015-06-09
    • Texas Instruments Incorporated
    • Erick Omar TorresByungchul Jang
    • H02M3/07H02M3/158H02M3/16H02M3/156H02M3/28H02M1/00
    • H02M3/07H02M3/156H02M3/1582H02M3/16H02M3/285H02M2001/009
    • A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout>a first Vout level and controls the BC to regulate to a second Vout level>the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.
    • 电荷泵降压转换器(CPBC)包括一个BC,它包括并联耦合的电感和CP。 控制逻辑耦合到耦合到电源开关的开关驱动器。 控制电路包括感测Vout的电压传感器和用于产生耦合到CP级的第一电压电平的电压传感器以及耦合到占空比/速率发生器模块的第二电压电平,该负载电平发生器模块向欠耦合 在OUT和控制逻辑之间。 当Vout>第一Vout电平时,控制电路禁用CP,并且控制BC调节到第一Vout电平>第一Vout电平。 如果Vout下降到UV阈值以下,在上电期间CP和BC之间的切换期间,UV监视器块修改施加到控制逻辑的输入,以增加提供给电感器的充电。