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1. 发明授权

US10340935B1 Thermometer digital to analog converter 有权
公开(公告)号：US10340935B1
公开(公告)日：2019-07-02
申请号：US15869617
申请日：2018-01-12
申请人： Dialog Semiconductor (UK) Limited
发明人： Hirohisa Tanabe , Seiichi Ozawa
IPC分类号： H03M1/10 , H03M1/76
CPC分类号： H03M1/1071 , H03M1/765
摘要： A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.

2. 发明申请

US20180337647A1 LARGE INPUT SWING CIRCUIT, CORRESPONDING DEVICE AND METHOD 审中-公开
公开(公告)号：US20180337647A1
公开(公告)日：2018-11-22
申请号：US15982548
申请日：2018-05-17
申请人： STMicroelectronics S.r.l.
发明人： Stefano RAMORINI , Alberto CATTANI , Alessandro GASPARINI , Germano NICOLLINI
IPC分类号： H03F3/45 , H03M1/12 , H03M1/66
CPC分类号： H03F3/45192 , H03F2200/18 , H03M1/124 , H03M1/66 , H03M1/68 , H03M1/742 , H03M1/765
摘要： A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.

3. 发明申请

US20180152656A1 SOLID-STATE IMAGING DEVICE 审中-公开
公开(公告)号：US20180152656A1
公开(公告)日：2018-05-31
申请号：US15797085
申请日：2017-10-30
申请人： Renesas Electronics Corporation
发明人： Osamu MATSUMOTO , Fukashi MORISHITA
IPC分类号： H04N5/378 , H03M1/46
CPC分类号： H04N5/378 , H03M1/123 , H03M1/46 , H03M1/466 , H03M1/682 , H03M1/765 , H04N5/37455
摘要： Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.

4. 发明申请

US20180083648A1 DIGITAL TO ANALOG CONVERTER 审中-公开
公开(公告)号：US20180083648A1
公开(公告)日：2018-03-22
申请号：US15697233
申请日：2017-09-06
申请人： Apple Inc.
发明人： Baris Cagdaser , Derek K. Shaeffer , Hopil Bae , Jesse Aaron Richmond , Jie Won Ryu , Kingsuk Brahma , Mohammad B. Vahid Far , Shingo Hatanaka , Yafei Bi , Yuichi Okuda
IPC分类号： H03M1/78 , H03M1/76 , H03M1/74 , H03M1/68
CPC分类号： H03M1/785 , G09G2320/0276 , H03M1/682 , H03M1/747 , H03M1/765
摘要： A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.

5. 发明申请

US20180006660A1 LEVEL SHIFTER, DIGITAL-TO-ANALOG CONVERTER, AND BUFFER AMPLIFIER, AND SOURCE DRIVER AND ELECTRONIC DEVICE INCLUDING THE SAME 有权
公开(公告)号：US20180006660A1
公开(公告)日：2018-01-04
申请号：US15703324
申请日：2017-09-13
申请人： INNOAXIS CO., LTD
发明人： Hwi-Cheol KIM
IPC分类号： H03M1/78 , G11C19/00 , G09G3/20 , H03M7/00 , H03K19/0185
CPC分类号： H03M1/785 , G09G3/2092 , G09G2300/0408 , G09G2300/0828 , G09G2300/0871 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G11C19/00 , H03K19/018521 , H03M1/765 , H03M7/00
摘要： A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

6. 发明授权

US09791482B1 Power integrated circuit with autonomous limit checking of ADC channel measurements 有权
公开(公告)号：US09791482B1
公开(公告)日：2017-10-17
申请号：US15607683
申请日：2017-05-30
申请人： Active-Semi, Inc.
发明人： John H. Carpenter, Jr. , Brett E. Smith , Hiroshi Watanabe
IPC分类号： H01H85/00 , G01R19/25 , G05B15/02 , G05F1/66 , G05B11/28 , H02M1/08 , H02H3/08
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.

7. 发明授权

US09705402B1 Power loss protection integrated circuit 有权
公开(公告)号：US09705402B1
公开(公告)日：2017-07-11
申请号：US15201265
申请日：2016-07-01
申请人： Active-Semi, Inc.
发明人： John H. Carpenter, Jr. , Brett E. Smith , Hiroshi Watanabe
IPC分类号： H02M3/158 , H02M1/32 , H02M1/08 , H02M3/156 , H02M1/00
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.

8. 发明授权

US09583241B1 Programmable impedance 有权
标题翻译：可编程阻抗
公开(公告)号：US09583241B1
公开(公告)日：2017-02-28
申请号：US14823843
申请日：2015-08-11
申请人： ANALOG DEVICES GLOBAL
发明人： Dennis A. Dempsey
IPC分类号： H03M1/66 , H01C13/00
CPC分类号： H03M1/765
摘要： The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.
摘要翻译：本申请一般涉及可编程阻抗，并且采用与主可编程阻抗并联的辅助阻抗，以在较低阻抗值下增加主可编程阻抗的性能。

9. 发明授权

US09559718B2 D/A conversion circuit, oscillator, electronic apparatus, and moving object 有权
标题翻译： D / A转换电路，振荡器，电子设备和移动物体
公开(公告)号：US09559718B2
公开(公告)日：2017-01-31
申请号：US15013132
申请日：2016-02-02
申请人： Seiko Epson Corporation
发明人： Akihiro Fukuzawa
IPC分类号： H03M1/66 , H03M1/76 , H01L23/528
CPC分类号： H03M1/76 , H01L23/528 , H01L27/0207 , H03M1/765
摘要： A D/A conversion circuit includes a plurality of resistors that are formed on a semiconductor substrate and that are connected in series to each other and a plurality of switches that are connected to the plurality of resistors, respectively, in which the plurality of resistors are configured using resistive element and a plurality of contacts that are provided to the resistive element, in which the plurality of switches are arranged side by side along a first direction when the semiconductor substrate is viewed from above, in which distances in the first direction between the plurality of contacts are equal to each other, and in which lengths in a second direction that is perpendicular to the first direction, of the plurality of resistors are unequal to each other.
摘要翻译： AD / A转换电路包括形成在半导体衬底上并且彼此串联连接的多个电阻器和分别连接到多个电阻器的多个电阻器的多个开关，其中多个电阻器被配置使用电阻元件和设置到电阻元件的多个触点，其中当从上方观察半导体衬底时，多个开关沿着第一方向并排布置，其中在多个开关之间的第一方向上的距离的触点彼此相等，并且在多个电阻器的垂直于第一方向的第二方向上的长度彼此不相等。

10. 发明申请

US20160379695A1 DIGITALLY TRIMMABLE INTEGRATED RESISTORS INCLUDING RESISTIVE MEMORY ELEMENTS 有权
标题翻译：包括电阻记忆元件在内的数字电容式集成电阻
公开(公告)号：US20160379695A1
公开(公告)日：2016-12-29
申请号：US14750670
申请日：2015-06-25
申请人： Intel Corporation
发明人： Jaydeep P. Kulkarni , Ashoke Ravi , Dinesh Somasekhar , Ganesh Balamurugan , Sudip Shekhar , Tawfiq Musah , Tzu-Chien Hsueh
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/161 , G05F3/00 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C2213/74 , G11C2213/79 , G11C2213/82 , H03H11/22 , H03K3/356104 , H03K19/018557 , H03K19/018585 , H03M1/12 , H03M1/362 , H03M1/66 , H03M1/765 , H04L25/00
摘要： Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (Mils). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.
摘要翻译：实施例包括耦合在信号路径上的电阻器，其包括一个或多个电阻性存储器元件，诸如一个或多个磁性隧道结（Mils）。电阻式存储器元件的电阻可以被数字可修整以调节电阻器在信号路径上的电阻。电阻器可以并入到模拟或混合信号电路中，以在信号路径上传递模拟信号。可以描述和要求保护其他实施例。

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