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21. 发明授权

US07656709B2 NAND step up voltage switching method 有权
标题翻译： NAND升压电压切换方式
公开(公告)号：US07656709B2
公开(公告)日：2010-02-02
申请号：US11800002
申请日：2007-05-03
申请人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
发明人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/145 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.
摘要翻译：具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

22. 发明授权

US07633786B2 Couplings within memory devices and methods 有权
标题翻译：内存设备和方法中的耦合
公开(公告)号：US07633786B2
公开(公告)日：2009-12-15
申请号：US11405762
申请日：2006-04-18
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C7/1036 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.
摘要翻译：提供了方法和装置。存储器件包括通过第一多路复用器门选择性地耦合到感测器件的输入的第一位线，以及通过第二复用器门选择性地耦合到感测器件的输入的第二位线。第一位线形成在第一垂直层并且耦合到第一多路复用器门的第一源/漏区。感测装置的输入形成在不同于第一垂直层的第二垂直层上，并且耦合到第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第一源极/漏极区域。第二位线形成在第一垂直层处，并且耦合到第二多路复用器门的第二源极/漏极区域。

23. 发明授权

US07372113B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07372113B2
公开(公告)日：2008-05-13
申请号：US10880508
申请日：2004-07-01
申请人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
发明人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
IPC分类号： H01L21/314
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/28282 , H01L21/28518 , H01L21/3185 , H01L21/76838 , H01L21/76897 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/792
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜，包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在下氮化硅膜比上述氮化硅膜高。

24. 发明授权

US07326993B2 Nonvolatile semiconductor memory and method for fabricating the same 失效
公开(公告)号：US07326993B2
公开(公告)日：2008-02-05
申请号：US10890132
申请日：2004-07-14
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788 , H01L23/522
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

25. 发明申请

US20080008006A1 Programming method for NAND EEPROM 有权
标题翻译： NAND EEPROM的编程方法
公开(公告)号：US20080008006A1
公开(公告)日：2008-01-10
申请号：US11900443
申请日：2007-09-12
申请人： Akira Goda , Seiichi Aritome , Todd Marquart
发明人： Akira Goda , Seiichi Aritome , Todd Marquart
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
摘要翻译：描述了NAND架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程在编程周期。在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。

26. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

27. 发明授权

US07006379B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07006379B2
公开(公告)日：2006-02-28
申请号：US11068228
申请日：2005-03-01
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
摘要翻译：一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导，关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

28. 发明授权

US06958938B2 Data writing method for semiconductor memory device and semiconductor memory device 有权
标题翻译：半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US06958938B2
公开(公告)日：2005-10-25
申请号：US11007461
申请日：2004-12-09
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.
摘要翻译：半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。第一参考阈值电压被设置为不同于第二参考阈值电压。

29. 发明授权

US06925009B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06925009B2
公开(公告)日：2005-08-02
申请号：US10920355
申请日：2004-08-18
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
摘要翻译：一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导，关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

30. 发明申请

US20050157578A1 Semiconductor memory device 有权
公开(公告)号：US20050157578A1
公开(公告)日：2005-07-21
申请号：US11074801
申请日：2005-03-09
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C16/02 , G06F11/10 , G11C8/00 , G11C11/34 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/42 , G11C29/52 , H01L21/8247 , H01L27/00 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

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