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21. 发明申请

US20090323489A1 Apparatus and method for connecting interrupted recording 审中-公开
标题翻译：用于连接中断记录的装置和方法
公开(公告)号：US20090323489A1
公开(公告)日：2009-12-31
申请号：US12003070
申请日：2007-12-19
申请人： Wen-Yi Wu , Hong-Ching Chen
发明人： Wen-Yi Wu , Hong-Ching Chen
IPC分类号： G11B5/09
CPC分类号： G11B27/24 , G11B20/1217 , G11B27/3027 , G11B2020/1277 , G11B2220/216 , G11B2220/218 , G11B2220/2562
摘要： An optical recording device records data on an optical storage medium. The device generates a data-interrupted address and reconnects the interrupted data from a data-reconnecting address so as to enable further correct reading of the interrupted data. The device comprises an addressing module for providing a reference address on the storage medium as a reference address; a recording-interrupted generator for detecting a recording-interrupted condition and generating a recording-interrupted signal; a data recording module for recording and suspending recording the data according to the recording-interrupted signal, and reconnecting the data according to a data-reconnecting address and the reference address; a data-interrupted address generator for generating the data-interrupted address; a data-reconnecting address generator for generating the data-reconnecting address.
摘要翻译：光记录装置在光存储介质上记录数据。该设备生成数据中断的地址，并重新连接数据重新连接地址中断的数据，以便进一步正确读取中断的数据。该设备包括用于在存储介质上提供参考地址作为参考地址的寻址模块; 用于检测记录中断状态并产生记录中断信号的记录中断发生器; 数据记录模块，用于根据记录中断信号记录和暂停记录数据，并根据数据重连地址和参考地址重新连接数据; 用于产生数据中断地址的数据中断地址发生器; 用于产生数据重新连接地址的数据重连地址发生器。

22. 发明授权

US07581160B2 ACS circuit and Viterbi decoder with the circuit 有权
标题翻译： ACS电路和维特比解码器与电路
公开(公告)号：US07581160B2
公开(公告)日：2009-08-25
申请号：US11527676
申请日：2006-09-27
申请人： Hong-Ching Chen , Wen-Zen Shen , Der-Tsuey Shen Wang, legal representative
发明人： Hong-Ching Chen , Wen-Zen Shen
IPC分类号： H03M13/41
CPC分类号： H03M13/6343 , H03M13/4107
摘要： An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.
摘要翻译：一个ACS电路和一个维特比解码器与电路。加法比较选择（ACS）电路包括：用于存储两个先前候选状态度量的两个寄存器; 第一加法器，用于将存储在第一寄存器中的值与第一分支度量相加以产生第一相加结果; 第二加法器，用于将存储在第二寄存器中的值与第一分支度量相加以产生第二相加结果; 比较器，用于比较存储在第一寄存器和第二寄存器中的值以产生判定位; 以及多路复用器，用于根据判定位选择第一相加结果或第二相加结果作为新的输出候选状态度量。由于加法器和比较器的并行处理，具有ACS的维特比解码器的处理速度将增加。

23. 发明申请

US20080209119A1 METHODS AND SYSTEMS FOR GENERATING ERROR CORRECTION CODES 审中-公开
标题翻译：用于产生错误校正码的方法和系统
公开(公告)号：US20080209119A1
公开(公告)日：2008-08-28
申请号：US12116220
申请日：2008-05-07
申请人： Hong-Ching Chen
发明人： Hong-Ching Chen
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： H03M13/2909 , H03M13/1515 , H03M13/2903
摘要： Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns of the data block, and Y is greater than or equal to 2. A second buffer stores Y partial-parity columns. An encoder is used for encoding the first section read from the first buffer to generate the partial-parity columns, and then storing the partial-parity columns in the second buffer. The second section read from the first buffer and the partial-parity columns read from the second buffer are encoded to generate updated partial-parity columns. Next, the partial-parity columns in the second buffer are updated by storing the updated partial-parity columns.
摘要翻译：用于生成ECC的方法和系统对数据块进行编码以产生相应的纠错码。第一缓冲器顺序地存储数据块的第一部分和第二部分，其中第一部分和第二部分中的每一个由数据块的X个数据行和Y个数据列组成，并且Y大于或等于2。第二缓冲器存储Y个部分奇偶校验列。编码器用于对从第一缓冲器读取的第一部分进行编码以产生部分奇偶校验列，然后将部分奇偶校验列存储在第二缓冲器中。从第一缓冲器读取的第二部分和从第二缓冲器读取的部分奇偶校验位被编码以生成更新的部分奇偶校验列。接下来，通过存储更新的部分奇偶校验列来更新第二缓冲器中的部分奇偶校验列。

24. 发明授权

US07234102B2 Data recording method for optical disk drive 有权
标题翻译：光盘驱动器的数据记录方法
公开(公告)号：US07234102B2
公开(公告)日：2007-06-19
申请号：US10711381
申请日：2004-09-15
申请人： Yih-Shin Weng , Hong-Ching Chen
发明人： Yih-Shin Weng , Hong-Ching Chen
IPC分类号： G06F11/00
CPC分类号： G11B20/10527 , G11B27/36 , G11B2020/1062 , G11B2020/10814 , G11B2020/10972 , G11B2220/2537 , G11B2220/2562
摘要： A data recording method for an optical disk drive is implemented by the following steps. First, one or more data blocks are encoded and recorded sequentially, and it detects if a buffer under run occurs. If a buffer under run occurs, the recording does not stop immediately until at least the main data of the data block being currently recorded have been recorded completely. Afterwards, it restarts to encode and record from the data block next to the data block where the recording stops. Moreover, the recording also can stops if a servo error is detected, and the data restart to encode and record from the data block where the recording stops or at least one data block preceding the data block where the recording stops.
摘要翻译：通过以下步骤实现光盘驱动器的数据记录方法。首先，一个或多个数据块被顺序地编码和记录，并且它检测是否发生运行缓冲器。如果发生运行中的缓冲区，则至少在当前记录的数据块的主数据已被完全记录之前，记录不会立即停止。之后，它重新开始编码和记录从记录停止的数据块旁边的数据块。此外，如果检测到伺服错误，则记录也可以停止，并且数据重新开始以从记录停止的数据块或者记录停止的数据块之前的至少一个数据块进行编码和记录。

25. 发明授权

US07205847B2 Phase locked loop for controlling an optical recording device and method thereof 有权
标题翻译：用于控制光学记录装置的锁相环及其方法
公开(公告)号：US07205847B2
公开(公告)日：2007-04-17
申请号：US11383754
申请日：2006-05-16
申请人： Hong-Ching Chen , Chi-Ming Chang
发明人： Hong-Ching Chen , Chi-Ming Chang
IPC分类号： H03L7/87 , G11B5/09
CPC分类号： H03L7/087 , G11B20/1426 , G11B2220/216 , G11B2220/218 , G11B2220/2562 , H03L7/197
摘要： A phase locked loop (PLL) system for generating a reference clock to write recording data on an optical medium includes a clock generator generating the reference clock according to a phase difference between the reference signal and a first frequency-divided signal; a phase-shift detector generating a phase adjusting signal; and a phase-controllable frequency divider dividing the frequency of the reference clock to generate the first frequency-divided signal, and receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal. The phase-shift detector includes an ADIP sync detector generating an ADIP synchronization signal synchronous to the ADIP units of the optical medium; a frequency divider dividing the reference clock to generate a second frequency-divided signal; and a phase difference detector detecting a phase difference between the second frequency-divided signal and the ADIP synchronization signal to generate the phase adjusting signal.
摘要翻译：用于产生用于在光学介质上写入记录数据的参考时钟的锁相环（PLL）系统包括：时钟发生器，其根据参考信号和第一分频信号之间的相位差产生参考时钟; 产生相位调整信号的相移检测器; 以及相位可控分频器，分频基准时钟的频率，生成第一分频信号，接收相位调整信号，调整第一分频信号的相位。相移检测器包括产生与光学介质的ADIP单元同步的ADIP同步信号的ADIP同步检测器; 分频器分配参考时钟以产生第二分频信号; 以及相位差检测器，检测第二分频信号和ADIP同步信号之间的相位差，以产生相位调整信号。

26. 发明申请

US20070002705A1 WRITE POWER CALIBRATING APPARATUS AND RELATED METHOD THEREOF 审中-公开
标题翻译：写功率校准装置及其相关方法
公开(公告)号：US20070002705A1
公开(公告)日：2007-01-04
申请号：US11160654
申请日：2005-07-04
申请人： Kuo-Ting Hsin , Hong-Ching Chen
发明人： Kuo-Ting Hsin , Hong-Ching Chen
IPC分类号： G11B7/12
CPC分类号： G11B7/1267
摘要： A write power calibrating method and related apparatus for determining an optimum write power used for recording data onto a digital versatile disc is disclosed. The write power calibrating method includes recording a plurality of first data sets onto the digital versatile disc by utilizing a plurality of different write powers respectively; executing an parity code decoding procedure on a plurality of second data sets read from the digital versatile disc to determine a plurality of byte error numbers detected by utilizing a parity code of each of the second data sets, the second data sets corresponding to the first data sets written onto the digital versatile disc; and determining the optimum write power according to the byte error numbers of the second data sets.
摘要翻译：公开了用于确定用于将数据记录到数字通用盘上的最佳写入功率的写功率校准方法和相关装置。写功率校准方法包括分别通过利用多个不同的写功率将多个第一数据组记录到数字通用盘上; 对从数字通用盘读取的多个第二数据集执行奇偶校验码解码过程，以确定通过利用每个第二数据集的奇偶校验码检测的多个字节错误编号，对应于第一数据的第二数据集写入数字多功能光盘; 以及根据第二数据集的字节错误数确定最佳写入功率。

27. 发明申请

US20050071732A1 DATA RECORDING METHOD FOR OPTICAL DISK DRIVE 有权
标题翻译：光盘驱动器的数据记录方法
公开(公告)号：US20050071732A1
公开(公告)日：2005-03-31
申请号：US10711381
申请日：2004-09-15
申请人： Yih-Shin Weng , Hong-Ching Chen
发明人： Yih-Shin Weng , Hong-Ching Chen
IPC分类号： G11B20/10 , G11B27/36 , G11C29/00 , H03M13/00
CPC分类号： G11B20/10527 , G11B27/36 , G11B2020/1062 , G11B2020/10814 , G11B2020/10972 , G11B2220/2537 , G11B2220/2562
摘要： A data recording method for an optical disk drive is implemented by the following steps. First, one or more data blocks are encoded and recorded sequentially, and it detects if a buffer under run occurs. If a buffer under run occurs, the recording does not stop immediately until at least the main data of the data block being currently recorded have been recorded completely. Afterwards, it restarts to encode and record from the data block next to the data block where the recording stops. Moreover, the recording also can stops if a servo error is detected, and the data restart to encode and record from the data block where the recording stops or at least one data block preceding the data block where the recording stops.
摘要翻译：通过以下步骤实现光盘驱动器的数据记录方法。首先，一个或多个数据块被顺序地编码和记录，并且它检测是否发生运行缓冲器。如果发生运行中的缓冲区，则至少在当前记录的数据块的主数据已被完全记录之前，记录不会立即停止。之后，它重新开始编码和记录从记录停止的数据块旁边的数据块。此外，如果检测到伺服错误，则记录也可以停止，并且数据重新开始以从记录停止的数据块或者记录停止的数据块之前的至少一个数据块进行编码和记录。

28. 发明授权

US08447917B2 Flash memory devices and methods for controlling a flash memory device 有权
标题翻译：闪存设备和用于控制闪存设备的方法
公开(公告)号：US08447917B2
公开(公告)日：2013-05-21
申请号：US12721724
申请日：2010-03-11
申请人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
发明人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.
摘要翻译：闪存器件包括存储器阵列和存储器控制电路。存储器阵列包括存储器模块。每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

29. 发明授权

US08074040B2 Flash device and method for improving performance of flash device 有权
标题翻译：闪存设备和提高闪存设备性能的方法
公开(公告)号：US08074040B2
公开(公告)日：2011-12-06
申请号：US12481764
申请日：2009-06-10
申请人： Hong-Ching Chen
发明人： Hong-Ching Chen
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.
摘要翻译：本发明提供一种闪光装置。在一个实施例中，闪存器件包括第一NAND闪存集成电路，第二NAND闪存集成电路和控制集成电路。控制集成电路产生具有第一定时的多个第一存取信号以访问第一NAND闪存IC，并且产生具有第二定时的多个第二存取信号以访问第二NAND闪存IC，其中第一定时不同于第二时间然后，第一NAND闪存集成电路根据第一接入信号访问存储在其中的数据。然后，第二NAND闪存集成电路根据第二存取信号访问存储在其中的数据。

30. 发明授权

US08013654B1 Clock generator, pulse generator utilizing the clock generator, and methods thereof 有权
标题翻译：时钟发生器，利用时钟发生器的脉冲发生器及其方法
公开(公告)号：US08013654B1
公开(公告)日：2011-09-06
申请号：US12336539
申请日：2008-12-17
申请人： Hong-Ching Chen , Chang-Po Ma
发明人： Hong-Ching Chen , Chang-Po Ma
IPC分类号： G06F1/04
CPC分类号： H03K5/15013 , G06F1/06 , G06F1/10
摘要： A clock generator for generating a first target clock signal includes: a control circuit, receiving a reference clock signal, and for generating a first clock enable signal and a first delay selecting signal according to the reference clock signal; a first clock gating unit, coupled to the control circuit, for receiving the reference clock signal and the first clock enable signal, and for passing the reference clock signal according to the first clock enable signal to generate a first clock gated signal; and a first delay module, coupled to the first clock gating unit, for delaying the first clock gated signal according to the first delay selecting signal to generate the first target clock signal.
摘要翻译：用于产生第一目标时钟信号的时钟发生器包括：控制电路，接收参考时钟信号，并用于根据参考时钟信号产生第一时钟使能信号和第一延迟选择信号; 第一时钟门控单元，耦合到控制电路，用于接收参考时钟信号和第一时钟使能信号，并且用于根据第一时钟使能信号传递参考时钟信号以产生第一时钟门控信号; 以及耦合到所述第一时钟门控单元的第一延迟模块，用于根据所述第一延迟选择信号延迟所述第一时钟门控信号以产生所述第一目标时钟信号。

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