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1. 发明授权

US08447917B2 Flash memory devices and methods for controlling a flash memory device 有权
标题翻译：闪存设备和用于控制闪存设备的方法
公开(公告)号：US08447917B2
公开(公告)日：2013-05-21
申请号：US12721724
申请日：2010-03-11
申请人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
发明人： Yeow-Chyi Chen , Hong-Ching Chen , Li-Chun Tu , Tzu-Chieh Lin , Chi-Wei Peng
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.
摘要翻译：闪存器件包括存储器阵列和存储器控制电路。存储器阵列包括存储器模块。每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

2. 发明授权

US08074040B2 Flash device and method for improving performance of flash device 有权
标题翻译：闪存设备和提高闪存设备性能的方法
公开(公告)号：US08074040B2
公开(公告)日：2011-12-06
申请号：US12481764
申请日：2009-06-10
申请人： Hong-Ching Chen
发明人： Hong-Ching Chen
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.
摘要翻译：本发明提供一种闪光装置。在一个实施例中，闪存器件包括第一NAND闪存集成电路，第二NAND闪存集成电路和控制集成电路。控制集成电路产生具有第一定时的多个第一存取信号以访问第一NAND闪存IC，并且产生具有第二定时的多个第二存取信号以访问第二NAND闪存IC，其中第一定时不同于第二时间然后，第一NAND闪存集成电路根据第一接入信号访问存储在其中的数据。然后，第二NAND闪存集成电路根据第二存取信号访问存储在其中的数据。

3. 发明授权

US08013654B1 Clock generator, pulse generator utilizing the clock generator, and methods thereof 有权
标题翻译：时钟发生器，利用时钟发生器的脉冲发生器及其方法
公开(公告)号：US08013654B1
公开(公告)日：2011-09-06
申请号：US12336539
申请日：2008-12-17
申请人： Hong-Ching Chen , Chang-Po Ma
发明人： Hong-Ching Chen , Chang-Po Ma
IPC分类号： G06F1/04
CPC分类号： H03K5/15013 , G06F1/06 , G06F1/10
摘要： A clock generator for generating a first target clock signal includes: a control circuit, receiving a reference clock signal, and for generating a first clock enable signal and a first delay selecting signal according to the reference clock signal; a first clock gating unit, coupled to the control circuit, for receiving the reference clock signal and the first clock enable signal, and for passing the reference clock signal according to the first clock enable signal to generate a first clock gated signal; and a first delay module, coupled to the first clock gating unit, for delaying the first clock gated signal according to the first delay selecting signal to generate the first target clock signal.
摘要翻译：用于产生第一目标时钟信号的时钟发生器包括：控制电路，接收参考时钟信号，并用于根据参考时钟信号产生第一时钟使能信号和第一延迟选择信号; 第一时钟门控单元，耦合到控制电路，用于接收参考时钟信号和第一时钟使能信号，并且用于根据第一时钟使能信号传递参考时钟信号以产生第一时钟门控信号; 以及耦合到所述第一时钟门控单元的第一延迟模块，用于根据所述第一延迟选择信号延迟所述第一时钟门控信号以产生所述第一目标时钟信号。

4. 发明授权

US08004939B2 Device and method for connecting interrupted recording 有权
标题翻译：连接中断录音的设备和方法
公开(公告)号：US08004939B2
公开(公告)日：2011-08-23
申请号：US12076644
申请日：2008-03-20
申请人： Wen-Yi Wu , Hong-Ching Chen
发明人： Wen-Yi Wu , Hong-Ching Chen
IPC分类号： G11B7/00
CPC分类号： G11B20/1217 , G11B7/0045 , G11B20/10425 , G11B20/1403 , G11B27/24 , G11B2020/10972 , G11B2020/1268 , G11B2020/1287 , G11B2220/216 , G11B2220/218 , G11B2220/2537
摘要： This invention provides an optical storage device for recording a plurality of data onto an optical storage medium. If recording interrupted, the optical storage device generates a data-interrupted address, and re-connects the interrupted data with a data re-connecting physical address. The optical storage device comprises a physical addressing module, a record-interrupt generator, a data recording controller, a data-interrupt address generator and a data-reconnecting physical address generator. The physical addressing module provides a reference physical address for recording data onto the optical storage medium. When detecting the interrupt of data recording, the data-interrupt address generator generates the address of the interrupted data. According to the address of the interrupted data, the data-reconnecting physical address generator generates a data-reconnecting physical address. The optical storage device utilizes the data-reconnecting physical address to continue to record the interrupted data onto the optical storage medium.
摘要翻译：本发明提供了一种用于将多个数据记录到光存储介质上的光存储装置。如果记录中断，光存储设备产生数据中断的地址，并重新连接中断的数据与数据重连物理地址。光学存储设备包括物理寻址模块，记录中断发生器，数据记录控制器，数据中断地址发生器和数据重新连接的物理地址发生器。物理寻址模块提供用于在光学存储介质上记录数据的参考物理地址。当检测到数据记录的中断时，数据中断地址发生器产生中断数据的地址。根据中断数据的地址，数据重新连接的物理地址发生器产生数据重新连接的物理地址。光学存储设备利用数据重新连接的物理地址继续将中断的数据记录到光学存储介质上。

5. 发明授权

US07773471B2 Recording apparatus and recording method 有权
标题翻译：记录装置和记录方法
公开(公告)号：US07773471B2
公开(公告)日：2010-08-10
申请号：US11532543
申请日：2006-09-18
申请人： Yih-Shin Weng , Wen-Yi Wu , Hong-Ching Chen
发明人： Yih-Shin Weng , Wen-Yi Wu , Hong-Ching Chen
IPC分类号： G11B27/10 , G11B7/00
CPC分类号： G11B7/00736 , G11B7/0045
摘要： A recording apparatus and a recording method are provided. Control information is generated by the microcontroller based on the received command. The data preparing unit has a control register and a preparing circuit, wherein the control register is used for storing a set of control register values corresponding to the control information, and the preparing circuit is used for generating prepared data based on the set of control register values and storing the prepared data in the data buffer. The recording circuit records on an optical storage media based on the prepared data. The optical storage media has a lead-in area having a plurality of continuous zones. The prepared data includes a plurality of data to be written into the corresponding zones and the plurality of data are stored in the data buffer in the same sequence as the writing sequence to the zones and are read continuously.
摘要翻译：提供了记录装置和记录方法。控制信息由微控制器基于接收的命令产生。数据准备单元具有控制寄存器和准备电路，其中控制寄存器用于存储对应于控制信息的一组控制寄存器值，并且准备电路用于基于该组控制寄存器产生准备好的数据值，并将准备的数据存储在数据缓冲器中。记录电路基于所准备的数据记录在光存储介质上。光存储介质具有多个连续区的导入区。所准备的数据包括要写入对应区域的多个数据，并且多个数据以与写入顺序相同的顺序存储在数据缓冲器中并连续读取。

6. 发明申请

US20070044008A1 ACS circuit and Viterbi decoder with the circuit 有权
标题翻译： ACS电路和维特比解码器与电路
公开(公告)号：US20070044008A1
公开(公告)日：2007-02-22
申请号：US11527676
申请日：2006-09-27
申请人： Hong-Ching Chen , Wen-Zen Shen , Der-Tsuey Shen Wang
发明人： Hong-Ching Chen , Wen-Zen Shen , Der-Tsuey Shen Wang
IPC分类号： H03M13/03
CPC分类号： H03M13/6343 , H03M13/4107
摘要： An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.
摘要翻译：一个ACS电路和一个维特比解码器与电路。加法比较选择（ACS）电路包括：用于存储两个先前候选状态度量的两个寄存器; 第一加法器，用于将存储在第一寄存器中的值与第一分支度量相加以产生第一相加结果; 第二加法器，用于将存储在第二寄存器中的值与第一分支度量相加以产生第二相加结果; 比较器，用于比较存储在第一寄存器和第二寄存器中的值以产生判定位; 以及多路复用器，用于根据判定位选择第一相加结果或第二相加结果作为新的输出候选状态度量。由于加法器和比较器的并行处理，具有ACS的维特比解码器的处理速度将增加。

7. 发明授权

US07075375B2 Phase locked loop for controlling an optical recording device and method thereof 失效
标题翻译：用于控制光学记录装置的锁相环及其方法
公开(公告)号：US07075375B2
公开(公告)日：2006-07-11
申请号：US10710934
申请日：2004-08-13
申请人： Hong-Ching Chen , Chi-Ming Chang
发明人： Hong-Ching Chen , Chi-Ming Chang
IPC分类号： H03L7/87 , G11B5/09
CPC分类号： H03L7/087 , G11B20/1426 , G11B2220/216 , G11B2220/218 , G11B2220/2562 , H03L7/197
摘要： A PLL system for generating an output signal according to a first reference signal is disclosed. The output signal is used as a reference clock to write recording data on an optical medium. The PLL system includes a clock generator for receiving the first reference signal and a first frequency-divided signal to generate the output signal according to a phase difference between the first reference signal and the first frequency-divided signal; a phase-shift detector for generating a phase adjusting signal; and a phase-controllable frequency divider for dividing the frequency of the output signal by a frequency dividing ratio to generate the first frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal.
摘要翻译：公开了一种用于根据第一参考信号产生输出信号的PLL系统。输出信号用作参考时钟，以在光学介质上写入记录数据。 PLL系统包括用于接收第一参考信号的时钟发生器和根据第一参考信号和第一分频信号之间的相位差产生输出信号的第一分频信号; 相移检测器，用于产生相位调整信号; 以及相位可控分频器，用于将输出信号的频率除以分频比，以产生第一分频信号，并用于接收相位调整信号以调整第一分频信号的相位。

8. 发明申请

US20060013095A1 Method and apparatus for detecting defects on optical disk 审中-公开
标题翻译：用于检测光盘上的缺陷的方法和装置
公开(公告)号：US20060013095A1
公开(公告)日：2006-01-19
申请号：US11183936
申请日：2005-07-19
申请人： Tun-Hsing Liu , Chun-Ying Chiang , Hong-Ching Chen
发明人： Tun-Hsing Liu , Chun-Ying Chiang , Hong-Ching Chen
IPC分类号： G11B7/00
CPC分类号： G11B7/00375
摘要： A defect detecting apparatus and a defect detecting method performs highly efficient and reliable defect detection over an optical disk. According to the defect detecting method, defect information is obtained during data recording. The necessity of data verification and the range of verification-demanding area are determined according to the defect information. The defect address is found efficiently by performing a data verification procedure over the verification-demanding area. The defect detecting method according to the present invention conducts data verification on defect-prone addresses instead performing a global examination for address areas recorded with data. Thereby, the defect detecting efficiency is enhanced.
摘要翻译：缺陷检测装置和缺陷检测方法在光盘上执行高效可靠的缺陷检测。根据缺陷检测方法，在数据记录期间获得缺陷信息。根据缺陷信息确定数据验证的必要性和验证要求区域的范围。通过在验证要求区域上执行数据验证程序来有效地发现缺陷地址。根据本发明的缺陷检测方法对缺陷多的地址进行数据验证，而是对记录有数据的地址区域执行全局检查。从而提高了缺陷检测效率。

9. 发明授权

US06794998B2 Data modulating/demodulating method and system and apparatus using the same 有权
公开(公告)号：US06794998B2
公开(公告)日：2004-09-21
申请号：US10272267
申请日：2002-10-15
申请人： Hong-Ching Chen
发明人： Hong-Ching Chen
IPC分类号： H03M700
CPC分类号： H03M5/145 , G11B20/1426
摘要： Data modulating/demodulating method and system and apparatus using the same. The modulation method with smaller modulation table, compared to the conventional modulation table, is used to modulate the source data to the channel bits to be recorded to an external storage apparatus, such as optical disc. The demodulation method with smaller demodulation table, compared to the conventional demodulation table, is used to demodulate the bit data stream recorded on a storage apparatus, such as optical disc, to the original source data.

10. 发明申请

US20110167323A1 Error-Correcting Apparatus and Method Thereof 审中-公开
标题翻译：误差校正装置及其方法
公开(公告)号：US20110167323A1
公开(公告)日：2011-07-07
申请号：US12683915
申请日：2010-01-07
申请人： Chih-Ching Yu , Pi-Hai Liu , Yu-Hsuan Lin , Chang-Long Wu , Hong-Ching Chen
发明人： Chih-Ching Yu , Pi-Hai Liu , Yu-Hsuan Lin , Chang-Long Wu , Hong-Ching Chen
IPC分类号： H03M13/41 , G06F11/10
CPC分类号： H03M13/4138 , H03M13/3707 , H03M13/373 , H03M13/3746
摘要： The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information.
摘要翻译：本发明公开了一种用于通过使用维特比算法对输入信号进行解码以产生包括擦除单元和解码器的维特比解码信号的纠错装置。擦除单元被配置为根据维特比算法中的路径度量的至少一个路径度量差产生至少一个逻辑信号，并且生成擦除信息，其中擦除信息指示维特比解码器的至少一个位置的数据可靠性信号。解码器被配置为根据擦除信息对维特比解码信号进行解码。

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