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21. 发明授权

US06519747B2 Method and apparatus for defining signal timing for an integrated circuit device 有权
标题翻译：用于定义集成电路器件的信号定时的方法和装置
公开(公告)号：US06519747B2
公开(公告)日：2003-02-11
申请号：US09837923
申请日：2001-04-18
申请人： Satyanarayana Nishtala , Jayarama N. Shenoy , Tai-Yu Chou , Michael C. Freda
发明人： Satyanarayana Nishtala , Jayarama N. Shenoy , Tai-Yu Chou , Michael C. Freda
IPC分类号： G06F945
CPC分类号： G06F17/5077 , G06F17/5031
摘要： One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.
摘要翻译：本发明的一个实施例提供了一种用于定义集成电路装置的信号定时的系统。该系统通过首先为集成电路设备创建虚拟定时参考平面来操作。然后，第一信号线从集成电路封装内的半导体管芯路由到集成电路封装的第一外部连接。接下来，系统从第一外部连接到虚拟定时参考平面生成用于印刷电路板上的第一电路迹线的第一逃逸模式。该第一逃逸模式指定从第一外部连接到印刷电路板到虚拟定时参考平面的路线。最后，该系统为虚拟定时参考平面上的第一信号线和第一电路迹线的组合建立第一组信号定时。

22. 发明授权

US06272007B1 Computer system cooling configuration 有权
标题翻译：电脑系统冷却配置
公开(公告)号：US06272007B1
公开(公告)日：2001-08-07
申请号：US09340962
申请日：1999-06-28
申请人： Kenneth Kitlas , Anita Patel , Satyanarayana Nishtala , Alan Lee Winick , Alan Lam , Winiie C. Leung , Kenneth A. Lown , Mohammed Tantoush
发明人： Kenneth Kitlas , Anita Patel , Satyanarayana Nishtala , Alan Lee Winick , Alan Lam , Winiie C. Leung , Kenneth A. Lown , Mohammed Tantoush
IPC分类号： G06F116
CPC分类号： G06F1/185 , G06F1/181 , G06F1/184 , G06F1/186 , G06F1/20
摘要： A computer system housing where a vertical printed circuit board, e.g., a riser card, is inserted into a socket on a computer system motherboard. Some internal space within the housing may allow optimization of system memory capacity through packing of additional memory modules on the riser card. The additional memory may be mounted on the riser card and may reside in the vertical space created between the riser card and the directly-mounted memory on the motherboard. The computer system housing further includes a chassis that may be partitioned into two separate sub-chassis for proper positioning of one or more cooling fans as well as to accommodate changes in computer system configurations with minimized retooling of the chassis. The cooling fans may be mounted at such locations on the chassis that allow optimization of air circulation and, hence, cooling within the housing. However, extra cooling fan(s) for the additional memory on the riser card may not be necessary in view of the creation of dedicated cooling channels within the housing by an efficient placement of the cooling fans. The optimization of fan placement within the housing results in efficient cooling of various system components and allows for increase in system component packing density without a similar increase in the number of cooling fans.
摘要翻译：一种将垂直印刷电路板（例如转接卡）插入计算机系统主板上的插座的计算机系统外壳。外壳内的一些内部空间可以通过在转接卡上包装附加的存储器模块来优化系统存储器容量。附加存储器可以安装在转接卡上，并且可以位于在转接卡和主板上直接安装的存储器之间产生的垂直空间中。计算机系统壳体还包括可以被划分成两个单独的子机架以用于一个或多个冷却风扇的适当定位的底盘，以及通过最小化底盘重新装配来适应计算机系统配置的变化。冷却风扇可以安装在底盘上的这样的位置，从而优化空气循环，从而优化壳体内的冷却。然而，考虑到通过冷却风扇的有效放置在壳体内创建专用冷却通道，可能不需要用于转接卡上的附加存储器的额外的冷却风扇。在壳体内优化风扇放置结果可以有效地冷却各种系统组件，并且可以增加系统组件的封装密度，而不会有类似的冷却风扇数量的增加。

23. 发明授权

US6101565A System for multisized bus coupling in a packet-switched computer system 失效
公开(公告)号：US6101565A
公开(公告)日：2000-08-08
申请号：US912772
申请日：1997-08-18
申请人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
发明人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
IPC分类号： G06F13/36 , G06F13/40 , G06F15/173 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

24. 发明授权

US5892957A Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system 失效
标题翻译：用于基于分组交换微处理器的计算机系统中的中断通信的方法和装置
公开(公告)号：US5892957A
公开(公告)日：1999-04-06
申请号：US868171
申请日：1997-06-03
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

25. 发明授权

US5710891A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5710891A
公开(公告)日：1998-01-20
申请号：US414559
申请日：1995-03-31
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器中进行仲裁发生在第二个时钟周期。

26. 发明授权

US5706463A Cache coherent computer system that minimizes invalidation and copyback operations 失效
标题翻译：缓存一致的计算机系统，使无效和副本操作最小化
公开(公告)号：US5706463A
公开(公告)日：1998-01-06
申请号：US854418
申请日：1997-05-12
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0815
摘要： A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.
摘要翻译：公开了一种多处理器计算机系统，其通过禁用用于不可能由请求处理器写入的数据的高速缓存一致性协议的第一写入优化来减少通过存储器互连的无效和复制操作的发生。这样的数据包括只读代码段。代码段（包括指令和数据）在多个处理器之间共享。请求处理器在只读数据块的高速缓存未命中时生成“读取共享始终”请求，否则生成“读取共享”请求。读共享始终请求将存储在高速缓冲存储器中的数据块中的结果标记为“共享”状态，而读共享请求导致数据块标记为“独占”状态。

27. 发明授权

US5689713A Method and apparatus for interrupt communication in a packet-switched computer system 失效
标题翻译：分组交换计算机系统中的中断通信的方法和装置
公开(公告)号：US5689713A
公开(公告)日：1997-11-18
申请号：US425537
申请日：1995-04-20
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

28. 发明授权

US5657472A Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor 失效
标题翻译：具有与每个处理器相关联的独立并行事务队列的多处理器系统的内存事务执行系统和方法
公开(公告)号：US5657472A
公开(公告)日：1997-08-12
申请号：US414922
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0828
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括主界面，用于向系统控制器发送存储器事务请求，以及从其他数据处理器接收来自系统控制器的对应于存储器事务请求的高速缓存访问请求。在优选实施例中，每个存储器事务请求被分类为两个不同的主类之一：包括读存储器访问请求的第一事务类和包括回写存储器访问请求的第二事务类。主接口和系统控制器具有对应的并行请求队列，每个主类一个，用于发送和接收存储器访问请求。系统控制器还包括用于处理每个存储器事务请求的存储器事务请求逻辑和具有一组重复高速缓存标签（Dtags）的重复高速缓存索引，包括与相关联的数据处理器中的每个主高速缓存标签相对应的一个高速缓存标签。

29. 发明授权

US5581729A Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：并行相干读写事务处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5581729A
公开(公告)日：1996-12-03
申请号：US414763
申请日：1995-03-31
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括具有用于向系统控制器发送存储器事务请求的主类的主接口。系统控制器包括用于由数据处理器处理每个存储器事务请求的存储器事务请求逻辑。系统控制器维护具有每个数据处理器的一组重复缓存标签（Dtags）的重复缓存索引。每个数据处理器具有用于存储先前存储在受害高速缓存行中的数据块的回写缓冲器，直到其各自的回写事务完成为止，以及用于存储与先前执行的读取事务相关联的高速缓存行的高速缓存状态的第N + 1个Dtag 到读写回事务对的相关回写事务。因此，在高速缓存未命中时，互连可以依赖于回写缓冲器或Nth + 1Dtag并行地执行读取和回写事务，以适应事务的任何排序。

30. 发明授权

US5181167A Stacking heatpipe for three dimensional electronic packaging 失效
标题翻译：堆叠热管用于三维电子包装
公开(公告)号：US5181167A
公开(公告)日：1993-01-19
申请号：US801672
申请日：1991-12-02
申请人： Howard L. Davidson , Satyanarayana Nishtala
发明人： Howard L. Davidson , Satyanarayana Nishtala
IPC分类号： F28D15/02 , G06F1/20 , H01L23/427 , H05K7/02 , H05K7/20
CPC分类号： H05K7/023 , F28D15/0233 , F28D15/04 , F28F2275/205
摘要： Heatpipe elements having a thin flat, rectangular geometry are contstructed according to known heatpipe techniques. An electronic circuit module incorporating multiple discrete and integrated circuit elements is integrally imbedded into a recessed top exterior surface of each heatpipe element. The heatpipe elements are longer in one dimension that the circuit modules imbedded therein, the excess length being partitioned equally on each side of a circuit module. The remaining opposing edges of each circuit module equally overhanging the lateral edges of the heatpipe are configured as area array connectors. The resultant heatpipe/circuit module forms bilateral thermal contact areas for thermally contacting complementary surfaces of immediately adjoining heatpipe/circuit modules. Circuit modules electrically contact preceding and succeeding circuit modules via stacking connectors interposed between the respective area array connectors. The thermal and electrical contact areas of each heatpipe/circuit module permit multiple heatpipe/circuit modules to be vertically stacked upon themselves permitting compact complex electronic systems producing moderate heat fluxes to be conveniently field-assembled and disassembled in any order consistent with the electronic systems' logic scheme, without necessitating special tools or demounting of liquid cooling connections.
摘要翻译：具有薄的扁平矩形几何形状的热管元件根据已知的热管技术被加强。包含多个分立和集成电路元件的电子电路模块被整体嵌入到每个热管元件的凹入的顶部外表面中。热管元件在嵌入其中的电路模块的一个维度上较长，多余的长度在电路模块的每一侧均匀分配。每个电路模块的与该热管的横向边缘同样伸出的相对边缘被配置为区域阵列连接器。所得的热管/电路模块形成用于热接触紧邻的热管/电路模块的互补表面的双向热接触区域。电路模块通过夹在相应的区域阵列连接器之间的堆叠连接器将前后电路模块电接触。每个热管/电路模块的热和电接触区域允许多个热管/电路模块垂直堆叠在自身上，从而允许紧凑的复杂电子系统产生适度的热通量，以便以与电子系统相关的任何顺序进行现场组装和拆卸，逻辑方案，不需要特殊工具或拆卸液体冷却连接。

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