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1. 发明授权

US08732506B2 Method and apparatus for providing power to a server platforms by using a capacitor to provide power during a second power supply transitioning on 有权
标题翻译：用于通过在第二电源转换期间使用电容器来提供电力来向服务器平台提供电力的方法和装置
公开(公告)号：US08732506B2
公开(公告)日：2014-05-20
申请号：US13116345
申请日：2011-05-26
申请人： Satyanarayana Nishtala , Mark Ramon Imbertson
发明人： Satyanarayana Nishtala , Mark Ramon Imbertson
IPC分类号： G06F1/30 , G06F1/00
CPC分类号： G06F1/28 , G06F1/3206 , G06F1/3287 , Y02D10/171
摘要： In one embodiment, a method includes determining if a power load requirement associated with a server arrangement is below a threshold. The server arrangement includes at least a first power supply and a second power supply, as well as a capacitor arrangement. The method also includes providing power to the server arrangement using the first power supply and not the second power supply when it is determined that the power load requirement is below the threshold, and providing the power to the server arrangement using the first power supply and the second power supply when it is determined that the power load requirement is not below the threshold.
摘要翻译：在一个实施例中，一种方法包括确定与服务器装置相关联的功率负载要求是否低于阈值。服务器装置至少包括第一电源和第二电源以及电容器装置。该方法还包括当确定电力负载要求低于阈值时使用第一电源而不是第二电源向服务器装置提供电力，并且使用第一电源向服务器装置提供电力，并且当确定电力负载要求不低于阈值时，第二电源。

2. 发明授权

US08117369B2 Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations 有权
标题翻译：用于在存储器模块插槽中操作的输入输出模块以及用于扩展用于输入 - 输出操作的存储器接口的方法
公开(公告)号：US08117369B2
公开(公告)日：2012-02-14
申请号：US12986104
申请日：2011-01-06
申请人： Satyanarayana Nishtala , Thomas Lee Lyon , Daniel Edward Lenoski
发明人： Satyanarayana Nishtala , Thomas Lee Lyon , Daniel Edward Lenoski
IPC分类号： G06F13/00 , H05K7/10
CPC分类号： G06F13/385 , G11C5/04
摘要： An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indicate one or more functions associated with the I/O module. The I/O module may also include a serial data controller to communicate serial data in accordance with a predetermined communication technique with a configurable switch of a host system over preselected system management (SM) bus address lines and unused system clock signal lines of the memory module socket. The predetermined communication technique may include a peripheral component interconnect express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached Small Computer System Interface (SAS), a universal-serial bus (USB) or a switched-fabric (InfiniBand) communication technique.
摘要翻译：配置为在存储器模块插座中操作的I / O模块和用于扩展存储器接口的方法一般在此描述。 I / O模块可以包括串行存在检测（SPD）设备，以指示I / O模块是I / O设备并且指示与I / O模块相关联的一个或多个功能。 I / O模块还可以包括串行数据控制器，以根据预定的通信技术，通过主机系统的可配置开关，通过预选的系统管理（SM）总线地址线和存储器的未使用的系统时钟信号线来传送串行数据模块插座。预定的通信技术可以包括外围组件互连快速（PCIe），串行高级技术附件（SATA），串行附属小型计算机系统接口（SAS），通用串行总线（USB）或交换结构（InfiniBand ）通信技术。

3. 发明授权

US07886103B2 Input-output module, processing platform and method for extending a memory interface for input-output operations 有权
标题翻译：输入输出模块，处理平台和扩展用于输入输出操作的存储器接口的方法
公开(公告)号：US07886103B2
公开(公告)日：2011-02-08
申请号：US12206501
申请日：2008-09-08
申请人： Satyanarayana Nishtala , Thomas L. Lyon , Daniel E. Lenoski
发明人： Satyanarayana Nishtala , Thomas L. Lyon , Daniel E. Lenoski
IPC分类号： H05K7/10 , G06F13/00
CPC分类号： G06F13/385 , G11C5/04
摘要： Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.
摘要翻译：这里一般地描述用于扩展存储器接口的I / O模块，处理平台和方法的实施例。在一些实施例中，I / O模块可以被配置为在诸如DIMM插槽的存储器模块插座中操作，以在主机系统中提供增加的I / O功能。一些系统管理总线地址线和一些未使用的系统时钟信号线可以被重新配置为用于I / O模块和主机系统的PCIe交换机之间的串行数据通信的串行数据线。

4. 发明申请

US20090177849A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

5. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

6. 发明授权

US5655100A Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务执行的事务激活处理器
公开(公告)号：US5655100A
公开(公告)日：1997-08-05
申请号：US414772
申请日：1995-03-31
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

7. 发明授权

US08825965B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08825965B2
公开(公告)日：2014-09-02
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00 , G06F13/42 , G06F13/16 , G06F12/02 , G06F12/06
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

8. 发明授权

US08621132B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08621132B2
公开(公告)日：2013-12-31
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

9. 发明申请

US20130091321A1 METHOD AND APPARATUS FOR UTILIZING NAND FLASH IN A MEMORY SYSTEM HIERARCHY 审中-公开
标题翻译：用于在存储器系统层级中使用NAND闪存的方法和装置
公开(公告)号：US20130091321A1
公开(公告)日：2013-04-11
申请号：US13270442
申请日：2011-10-11
申请人： Satyanarayana Nishtala , Pere Monclus
发明人： Satyanarayana Nishtala , Pere Monclus
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F2212/2024 , G06F2212/205
摘要： In one embodiment, a method includes obtaining a request for data, determining if the data is present in a physical memory, and obtaining the data from a non-volatile random access memory if it is determined that the data is not present in the physical memory. The request is obtained by an overall system that includes the physical memory and the non-volatile random access memory, and the overall system is configured to push information from the physical memory to the non-volatile random access memory.
摘要翻译：在一个实施例中，一种方法包括获得对数据的请求，确定数据是否存在于物理存储器中，以及如果确定数据不存在于物理存储器中，则从非易失性随机存取存储器获取数据。该请求由包括物理存储器和非易失性随机存取存储器的整个系统获得，并且整个系统被配置为将信息从物理存储器推送到非易失性随机存取存储器。

10. 发明申请

US20100235662A1 SERVER POWER MANAGER AND METHOD FOR DYNAMICALLY MANAGING SERVER POWER CONSUMPTION 有权
标题翻译：服务器功率管理器和动态管理服务器功耗的方法
公开(公告)号：US20100235662A1
公开(公告)日：2010-09-16
申请号：US12634367
申请日：2009-12-09
申请人： Satyanarayana Nishtala
发明人： Satyanarayana Nishtala
IPC分类号： G06F1/32 , G06F9/455 , G06F12/08
CPC分类号： G06F1/3203 , G06F12/06 , G06F12/08
摘要： A server power manager and method for dynamic server power management are generally described herein. The server power manager is configured to implement one or more server management policies that identify target server power consumption and/or target functionality for the server system. The server power manager determines an amount of excess processing capability and/or an amount of excess physical memory based on the target server power consumption and the target functionality. The server power manager may transition a processor core to a lower-operational state when at least a predetermined amount of excess processing capability is determined while maintaining server system functionality. The server power manager may transition a memory module to a lower-operational state when at least a predetermined amount of excess physical memory is determined while maintaining the server system functionality.
摘要翻译：本文一般地描述用于动态服务器电源管理的服务器电源管理器和方法。服务器电源管理器被配置为实现识别服务器系统的目标服务器功耗和/或目标功能的一个或多个服务器管理策略。服务器电源管理器基于目标服务器功耗和目标功能来确定多余的处理能力和/或多余的物理存储器量。当在保持服务器系统功能的同时确定至少预定量的多余处理能力时，服务器功率管理器可以将处理器核心转换到较低操作状态。当在保持服务器系统功能的同时确定至少预定量的多余的物理存储器时，服务器电源管理器可以将存储器模块转换到较低的操作状态。

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