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21. 发明授权

US09343569B2 Vertical compound semiconductor field effect transistor on a group IV semiconductor substrate 有权
标题翻译：在IV族半导体衬底上的垂直化合物半导体场效应晶体管
公开(公告)号：US09343569B2
公开(公告)日：2016-05-17
申请号：US14283450
申请日：2014-05-21
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L29/66 , H01L21/00 , H01L21/84 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/823412 , H01L21/823487 , H01L21/8258 , H01L21/84 , H01L27/1207 , H01L29/66 , H01L29/66666 , H01L29/78
摘要： Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.
摘要翻译：可以在包括含有IV族半导体材料的手柄衬底的绝缘体上半导体衬底上形成IV族半导体器件。形成空腔以通过掩埋绝缘体层的堆叠，顶部半导体层中的掺杂半导体材料部分和电介质材料层物理地暴露手柄衬底的顶表面。通过介电材料层和各向异性蚀刻的共形沉积在腔周围形成栅极电介质。通过在沟槽中和/或之上的选择性外延工艺和从处理衬底的顶表面形成下有源区，沟道区和上有源区。选择性外延工艺沉积化合物半导体材料。掺杂半导体材料部分用作垂直化合物半导体场效应晶体管的栅极。

22. 发明申请

US20150357386A1 HYBRID BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译：混合双极性晶体管
公开(公告)号：US20150357386A1
公开(公告)日：2015-12-10
申请号：US14827266
申请日：2015-08-14
申请人： International Business Machines Corporation
发明人： Ali Afzali-Ardakani , Bahman Hekmatshoartabari , Tak H. Ning , Davood Shahrjerdi
IPC分类号： H01L27/32 , H01L29/73 , H01L29/10 , H01L27/12 , H01L29/08
CPC分类号： H01L27/286 , H01L27/1214 , H01L27/124 , H01L27/3225 , H01L27/3244 , H01L27/3274 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/66265 , H01L29/7302 , H01L29/7317 , H01L51/0055 , H01L51/0504 , H01L2227/323
摘要： Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
摘要翻译：包括无机通道和有机发射极结在内的双极结晶体管用于形成高分辨率有源矩阵显示器的一些应用中。这种双极结晶体管的阵列电连接到薄膜开关晶体管，并为无源器件（例如有机发光二极管）提供高驱动电流。

23. 发明申请

US20150340495A1 VERTICAL COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR ON A GROUP IV SEMICONDUCTOR SUBSTRATE 有权
标题翻译： IV族半导体衬底上的垂直化合物半导体场效应晶体管
公开(公告)号：US20150340495A1
公开(公告)日：2015-11-26
申请号：US14283450
申请日：2014-05-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/823412 , H01L21/823487 , H01L21/8258 , H01L21/84 , H01L27/1207 , H01L29/66 , H01L29/66666 , H01L29/78
摘要： Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor.
摘要翻译：可以在包括含有IV族半导体材料的手柄衬底的绝缘体上半导体衬底上形成IV族半导体器件。形成空腔以通过掩埋绝缘体层的堆叠，顶部半导体层中的掺杂半导体材料部分和电介质材料层物理地暴露手柄衬底的顶表面。通过介电材料层和各向异性蚀刻的共形沉积在腔周围形成栅极电介质。通过在沟槽中和/或之上的选择性外延工艺和从处理衬底的顶表面形成下有源区，沟道区和上有源区。选择性外延工艺沉积化合物半导体材料。掺杂半导体材料部分用作垂直化合物半导体场效应晶体管的栅极。

24. 发明申请

US20150279913A1 VERTICALLY INTEGRATED ACTIVE MATRIX BACKPLANE 审中-公开
标题翻译：垂直集成有源矩阵背板
公开(公告)号：US20150279913A1
公开(公告)日：2015-10-01
申请号：US14226285
申请日：2014-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen M. Gates , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/32 , H01L51/56
CPC分类号： H01L27/3248 , H01L27/1251 , H01L29/1604 , H01L29/42304 , H01L29/66242 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/737 , H01L29/8086
摘要： A method of forming an active matrix pixel that includes forming a driver device including contact regions deposited using a low temperature deposition process on a first portion of an insulating substrate. An electrode of an organic light emitting diode is formed on a second portion of the insulating substrate. The electrode is in electrical communication to receive an output from the driver device. At least one passivation layer is formed over the driver device. A switching device comprising at least one amorphous semiconductor layer is formed on the at least one passivation layer over the driver device.
摘要翻译：一种形成有源矩阵像素的方法，包括在绝缘基板的第一部分上形成包括使用低温沉积工艺沉积的接触区域的驱动器件。有机发光二极管的电极形成在绝缘基板的第二部分上。电极电连接以接收来自驱动器装置的输出。在驱动器装置上形成至少一个钝化层。包括至少一个非晶半导体层的开关器件形成在驱动器器件上的至少一个钝化层上。

25. 发明申请

US20150270187A1 FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES 有权
公开(公告)号：US20150270187A1
公开(公告)日：2015-09-24
申请号：US14732689
申请日：2015-06-06
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Wilfried E. Haensch , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L23/14 , H01L27/092 , H01L23/538 , H01L27/12
CPC分类号： H01L23/14 , H01L21/4846 , H01L21/7624 , H01L23/5381 , H01L23/5386 , H01L23/5387 , H01L27/092 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

26. 发明申请

US20150263064A1 PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR 有权
标题翻译：后照明图像传感器的钝化
公开(公告)号：US20150263064A1
公开(公告)日：2015-09-17
申请号：US14725151
申请日：2015-05-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/146
CPC分类号： H01L27/14692 , H01L27/1461 , H01L27/1462 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/14687
摘要： A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.
摘要翻译：用于形成背照式图像传感器的方法包括在晶体衬底上形成较高掺杂晶体层，在较高掺杂晶体层上生长较低掺杂晶体层，并从下部掺杂晶体层形成光电二极管和分量电路。形成金属化结构以形成与组件之间的连接。去除晶体衬底以暴露较高掺杂的晶体层。在较高掺杂晶体层的暴露表面上提供光学部件结构以在其中接收光，使得较高掺杂晶体层为光电二极管和部件电路提供钝化层。

27. 发明申请

US20150255664A1 HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD 审中-公开
标题翻译：异相光电器件和制造方法
公开(公告)号：US20150255664A1
公开(公告)日：2015-09-10
申请号：US14717284
申请日：2015-05-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Keith E. Fogel , Bahman Hekmatshoar-Tabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/18 , C23C14/34 , H01L31/0224 , H01L31/0216 , H01L31/0725 , H01L31/074
CPC分类号： H01L31/0725 , C23C14/3407 , H01L31/02167 , H01L31/022441 , H01L31/074 , H01L31/0747 , H01L31/078 , H01L31/1808 , H01L31/1812 , H01L31/204 , Y02E10/50 , Y02P70/521
摘要： A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
摘要翻译：光伏器件和方法包括掺杂的含锗衬底，在第一侧耦合到衬底的发射极触点和在与第一侧相对的一侧耦合到衬底的后触点。发射极包括与衬底相反的导电类型的至少一个掺杂层，而后接触包括至少一个与衬底相同导电类型的掺杂层。发射极接触的至少一个掺杂层或背接触的至少一个掺杂层与衬底直接接触，并且发射极接触或后接触的至少一个掺杂层包括n型材料具有小于衬底的电子亲和力，或具有大于衬底的孔亲合力的p型材料。

28. 发明申请

US20150249188A1 HETEROJUNCTION LIGHT EMITTING DIODE 有权
标题翻译：异位发光二极管
公开(公告)号：US20150249188A1
公开(公告)日：2015-09-03
申请号：US14711462
申请日：2015-05-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Tze-Chiang Chen , Bahman Hekmatshoartabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L33/30 , H01L33/00 , H01L33/62 , H01L33/18
CPC分类号： H01L33/0079 , H01L21/02546 , H01L33/0025 , H01L33/06 , H01L33/18 , H01L33/305 , H01L33/62 , H01L2924/10329
摘要： A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.
摘要翻译：一种用于形成发光器件的方法包括在单晶衬底上形成单晶III-V发光层，并在发光层上形成第一掺杂层。第一接触沉积在第一掺杂层上。通过机械过程从发射层去除单晶衬底。在发射层上形成第二掺杂层，该衬底已被去除。第二掺杂层具有与第一掺杂层相反的掺杂剂导电性。第二接触沉积在第二掺杂层上。

29. 发明授权

US09064698B1 Thin-film gallium nitride structures grown on graphene 有权
标题翻译：在石墨烯上生长的薄膜氮化镓结构
公开(公告)号：US09064698B1
公开(公告)日：2015-06-23
申请号：US14229936
申请日：2014-03-30
申请人： International Business Machines Corporation
发明人： Ali Khakifirooz , Davood Shahrjerdi
IPC分类号： H01L21/30 , H01L21/46 , H01L21/20 , H01L21/02
CPC分类号： H01L21/02444 , H01L21/02376 , H01L21/02378 , H01L21/02488 , H01L21/02502 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/20 , H01L21/7806 , H01L29/2003
摘要： Thin film gallium nitride structures are fabricated by providing a semiconductor-carbon alloy substrate having a dielectric layer on a surface of the substrate, forming trenches in the dielectric layer to expose surface portions of the surface of the substrate, and forming an epitaxial graphene layer on the exposed surface portions of the surface of the substrate. A buffer layer of rare earth metal oxide material is grown epitaxially on the graphene layer. Gallium nitride structures are formed epitaxially on the metal oxide/graphene layers and within the trenches of the dielectric layer, limiting defects by aspect ratio trapping. A stressor layer is formed over the nitride structures. Removing the substrate below the graphene layer allows the nitride structures to be placed on a surrogate substrate.
摘要翻译：通过在基板的表面上设置具有电介质层的半导体 - 碳合金基板来制造薄膜氮化镓结构，在电介质层中形成沟槽，以暴露基板表面的表面部分，并在其上形成外延石墨烯层衬底的表面的暴露的表面部分。在石墨烯层上外延生长稀土金属氧化物材料的缓冲层。在金属氧化物/石墨烯层和电介质层的沟槽内外延形成氮化镓结构，通过纵横比捕获限制缺陷。在氮化物结构上形成应力层。去除石墨烯层下面的基底允许将氮化物结构放置在替代基底上。

30. 发明授权

US09048363B2 Elemental semiconductor material contact for high indium content InGaN light emitting diodes 有权
标题翻译：元素半导体材料接触用于高铟含量的InGaN发光二极管
公开(公告)号：US09048363B2
公开(公告)日：2015-06-02
申请号：US13897507
申请日：2013-05-20
申请人： International Business Machines Corporation
发明人： Anirban Basu , Wilfried Haensch , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L33/06 , H01L29/15 , H01L33/00 , H01L33/32
CPC分类号： H01L33/06 , H01L33/0075 , H01L33/02 , H01L33/20 , H01L33/32 , H01L2933/0016
摘要： A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.
摘要翻译：包括p掺杂的GaN部分，包括氮化镓镓层的多量子阱和n掺杂的透明导电材料部分的垂直堆叠形成在绝缘体基板上。在垂直堆叠周围形成电介质材料衬垫，并被图案化以物理暴露p掺杂GaN部分的表面。采用选择性低温外延工艺将包含至少一种元素半导体材料的半导体材料沉积在p掺杂GaN部分的物理暴露表面上，从而形成元素半导体材料部分。选择性低温外延工艺可以在低于600℃的温度下进行，从而限制多量子阱内材料的扩散，并避免多量子阱内铟的偏析。发光二极管可以产生宽范围的辐射，包括可见光波长范围内的蓝光和绿光。

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