专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20090116280A1 Accessing a phase change memory 有权
标题翻译：访问相变存储器
公开(公告)号：US20090116280A1
公开(公告)日：2009-05-07
申请号：US11983098
申请日：2007-11-07
申请人： Ward Parkinson , Tyler Lowrey
发明人： Ward Parkinson , Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying a current to the phase change memory cell that is sufficient for the intended access operation and greater than that provided directly by the current source.
摘要翻译：存储器采用低电平电流源来访问相变存储器单元。电流源为存取电容器充电以便为接下来的存取储存足够的电量。当访问存储器单元时，存储在电容器上的电荷通过相变存储器放电，向相变存储器单元提供足以用于预期访问操作的电流并且大于由电流源直接提供的电流。

32. 发明申请

US20090109737A1 Method of restoring variable resistance memory device 有权
标题翻译：可变电阻存储器件的恢复方法
公开(公告)号：US20090109737A1
公开(公告)日：2009-04-30
申请号：US11981343
申请日：2007-10-31
申请人： Sergey A. Kostylev
发明人： Sergey A. Kostylev
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0033 , G11C16/3431 , G11C2013/0073
摘要： Methods of programming a phase-change memory device that remedy device failure. The methods includes applying a sequence of two or more electrical energy pulses to the device, where the sequence of pulses includes positive polarity pulses and negative polarity pulses. In one method, two or more pulses of an initial polarity are applied and are followed by one or more pulses having opposite polarity. In another method, pulses of an initial polarity are repeatedly applied until the device fails and one or more pulses of opposite polarity are subsequently applied to restore the device to its initial performance. The pulses may be set pulses, reset pulses, or pulses that produce programmed states having a resistance intermediate between the set resistance and reset resistance of the device.
摘要翻译：编程改变设备故障的相变存储器件的方法。所述方法包括将两个或多个电能脉冲的序列应用于该装置，其中脉冲序列包括正极性脉冲和负极性脉冲。在一种方法中，施加初始极性的两个或更多个脉冲，并且后跟一个或多个具有相反极性的脉冲。在另一种方法中，重复施加初始极性的脉冲，直到器件发生故障，并且随后施加相反极性的一个或多个脉冲以将器件恢复到初始性能。脉冲可以是产生编程状态的脉冲，复位脉冲或脉冲，其具有位于设备的设定电阻和复位电阻之间的电阻。

33. 发明授权

US07525117B2 Chalcogenide devices and materials having reduced germanium or telluruim content 有权
标题翻译：硫族化物装置和具有降低的锗或碲化物含量的材料
公开(公告)号：US07525117B2
公开(公告)日：2009-04-28
申请号：US11301211
申请日：2005-12-12
申请人： Sergey A. Kostylev , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj
发明人： Sergey A. Kostylev , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A chalcogenide material and memory device exhibiting fast operation over an extended range of reset state resistances. Electrical devices containing the chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio. The devices provide for high resistance contrast of memory states while preserving fast operational speeds. The chalcogenide materials include Ge, Sb and Te where the Ge and/or Te content is lean relative to Ge2Sb2Te5. In one embodiment, the concentration of Ge is between 11% and 22%, the concentration of Sb is between 22% and 65%, and the concentration of Te is between 28% and 55%. In a preferred embodiment, the concentration of Ge is between 15% and 18%, the concentration of Sb is between 32% and 35%, and the concentration of Te is between 48% and 51%.
摘要翻译：在扩展的复位状态电阻范围内呈现快速操作的硫族化物材料和存储器件。含有硫族化物材料的电气装置允许从复位状态到设定状态的快速转换以及具有高电阻比的设定状态。这些器件提供高电阻对比度的存储器状态，同时保持快速的操作速度。硫族化物材料包括Ge，Sb和Te，其中Ge和/或Te含量相对于Ge 2 Sb 2 Te 5是贫的。在一个实施方案中，Ge的浓度为11％至22％，Sb的浓度为22％至65％，Te的浓度为28％至55％。在优选的实施方案中，Ge的浓度为15％至18％，Sb的浓度为32％至35％，Te的浓度为48％至51％。

34. 发明申请

US20090065351A1 Method and apparatus for deposition 审中-公开
标题翻译：沉积方法和装置
公开(公告)号：US20090065351A1
公开(公告)日：2009-03-12
申请号：US11900326
申请日：2007-09-11
申请人： Robert Nuss
发明人： Robert Nuss
IPC分类号： C23C14/34
CPC分类号： C23C14/35 , C23C14/3492 , C23C14/548 , H01J37/3244 , H01J37/32449 , H01J37/3405
摘要： A deposition system supplies a continuous flow of process gases and sequentially selects among the flowing process gases for delivery to a reaction chamber. In the reaction chamber the delivered process gas acts as an ionizing species and thereby effects the deposition of a target substance upon a substrate. Gases not selected for delivery to the reaction chamber are swept away by a vacuum pump. By making a plurality of process gases continuously available, sequentially selecting among the available process gases, and pumping unused gases away before they enter the reaction chamber, such a system and method provides for continuous, sequential, uninterrupted deposition of a variety of substances, while maintaining desired flow rates and chamber pressures.
摘要翻译：沉积系统提供连续的工艺气体流并在流动的工艺气体中依次选择输送到反应室。在反应室中，所输送的工艺气体充当电离物质，从而影响目标物质沉积在基底上。没有选择用于输送到反应室的气体被真空泵扫除。通过连续获得多种工艺气体可用，在可用的工艺气体之间顺序地选择，并且在未使用的气体进入反应室之前抽出未使用的气体，这种系统和方法提供了各种物质的连续的，连续的，不间断的沉积，同时保持所需的流速和室压力。

35. 发明授权

US07426135B2 Static random access memory cell using chalcogenide 有权
标题翻译：使用硫属化物的静态随机存取存储单元
公开(公告)号：US07426135B2
公开(公告)日：2008-09-16
申请号：US11158619
申请日：2005-06-22
申请人： Tyler A Lowrey , Ward D. Parkinson
发明人： Tyler A Lowrey , Ward D. Parkinson
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C13/0004 , G11C13/0033 , G11C2213/79
摘要： A static random access memory may be formed using a bitline and a bitline bar coupled to ovonic threshold switches. The ovonic threshold switches may, in turn, be coupled to cross coupled NMOS transistors. In some embodiments, a very compact static random access memory may result.
摘要翻译：静态随机存取存储器可以使用位线和与椭圆形阈值开关耦合的位线条来形成。另外，所述超声阈值开关又可耦合到交叉耦合的NMOS晶体管。在一些实施例中，可能导致非常紧凑的静态随机存取存储器。

36. 发明授权

US07338857B2 Increasing adherence of dielectrics to phase change materials 有权
公开(公告)号：US07338857B2
公开(公告)日：2008-03-04
申请号：US10965129
申请日：2004-10-14
申请人： Paola Besana , Tina Marangon , Amos Galbiati
发明人： Paola Besana , Tina Marangon , Amos Galbiati
IPC分类号： H01L21/336
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608
摘要： A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.

37. 发明授权

US07327602B2 Methods of accelerated life testing of programmable resistance memory elements 失效
标题翻译：可编程电阻存储元件加速寿命测试方法
公开(公告)号：US07327602B2
公开(公告)日：2008-02-05
申请号：US10960263
申请日：2004-10-07
申请人： Sergey A. Kostylev , Tyler Lowrey , Wolodymyr Czubatyj
发明人： Sergey A. Kostylev , Tyler Lowrey , Wolodymyr Czubatyj
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C29/50 , G11C2013/0078 , G11C2013/0092
摘要： A method of testing a programmable resistance memory element. The method includes applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed to program the memory element from its set state to its reset state.
摘要翻译：一种测试可编程电阻存储元件的方法。该方法包括将多个复位脉冲施加到存储元件。每个复位脉冲具有大于将存储器元件从其设置状态编程到其复位状态所需的最小能量的能量。

38. 发明授权

US07253429B2 Electrically programmable memory element 有权
标题翻译：电可编程存储元件
公开(公告)号：US07253429B2
公开(公告)日：2007-08-07
申请号：US10981826
申请日：2004-11-05
申请人： Patrick Klersy , Tyler Lowrey
发明人： Patrick Klersy , Tyler Lowrey
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A programmable resistance memory element including a memory material which is raised above a semiconductor substrate by a dielectric layer.
摘要翻译：一种可编程电阻存储元件，包括通过电介质层在半导体衬底上升起的存储材料。

39. 发明授权

US07203087B2 Fast reading, low consumption memory device and reading method thereof 有权
标题翻译：快速阅读，低消耗记忆装置及其阅读方法
公开(公告)号：US07203087B2
公开(公告)日：2007-04-10
申请号：US11018550
申请日：2004-12-20
申请人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
发明人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.
摘要翻译：一种存储器件，具有读取配置，并且包括排列成行和列的多个存储器单元，布置在同一列上的存储器单元具有连接到相同位线的相应第一端子和布置在同一行上的存储器单元，该存储单元具有相应的第二端子可选择性地连接到相同的字线; 提供电源电压的电源线; 列寻址电路和行寻址电路，用于分别寻址与读取配置中读取的存储单元对应的位线和字线。列寻址电路被配置为在读取配置中基本上以电源电压偏置对应于所选存储单元的寻址位线。行驱动电路以非零字线读取电压偏置对应于所选存储单元的寻址字线，使得在第一端和第二端之间施加低于相变电压的预定电池电压读取配置中选定的存储单元。

40. 发明申请

US20070057341A9 Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured 失效
公开(公告)号：US20070057341A9
公开(公告)日：2007-03-15
申请号：US10824631
申请日：2004-04-14
申请人： Fabio Pellizzer
发明人： Fabio Pellizzer
IPC分类号： G11B33/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/101 , H01L27/2445 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式