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1. 发明授权

US09318699B2 Resistive memory cell structures and methods 有权
标题翻译：电阻记忆体结构和方法
公开(公告)号：US09318699B2
公开(公告)日：2016-04-19
申请号：US13352680
申请日：2012-01-18
申请人： Fabio Pellizzer , Ferdinando Bedeschi
发明人： Fabio Pellizzer , Ferdinando Bedeschi
IPC分类号： H01L21/20 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1641 , H01L45/165 , H01L45/1675 , H01L45/1683
摘要： Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.
摘要翻译：本文描述了电阻记忆单元结构和方法。一个或多个存储单元结构包括包含第一电阻可变材料的第一电阻式存储单元和包括不同于第一电阻可变材料的第二电阻可变材料的第二电阻式存储单元。

2. 发明申请

US20130181183A1 RESISTIVE MEMORY CELL STRUCTURES AND METHODS 有权
公开(公告)号：US20130181183A1
公开(公告)日：2013-07-18
申请号：US13352680
申请日：2012-01-18
申请人： Fabio Pellizzer , Ferdinando Bedeschi
发明人： Fabio Pellizzer , Ferdinando Bedeschi
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1641 , H01L45/165 , H01L45/1675 , H01L45/1683
摘要： Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

3. 发明申请

US20130010533A1 DESCENDING SET VERIFY FOR PHASE CHANGE MEMORY 有权
标题翻译：相机更改存储器的下载套件验证
公开(公告)号：US20130010533A1
公开(公告)日：2013-01-10
申请号：US13511987
申请日：2009-12-29
申请人： Ferdinando Bedeschi
发明人： Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
摘要翻译：本文公开的主题涉及存储器件，更具体地涉及写入相变存储器的性能。

4. 发明申请

US20120268984A1 Adaptive Wordline Programming Bias of a Phase Change Memory 有权
标题翻译：相变存储器的自适应字线编程偏置
公开(公告)号：US20120268984A1
公开(公告)日：2012-10-25
申请号：US13535623
申请日：2012-06-28
申请人： Richard E. Fackenthal , Ferdinando Bedeschi , Meenatchi Jagasivamani , Ravi Annavajjhala , Enzo M. Donze
发明人： Richard E. Fackenthal , Ferdinando Bedeschi , Meenatchi Jagasivamani , Ravi Annavajjhala , Enzo M. Donze
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , Y10S977/754
摘要： The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
摘要翻译：可以使用自适应字线偏置来减小相变存储器的漏电流和功耗。根据施加到编程单元的位线的特定电压，未选择的单元的字线可能相应地变化。在一些实施例中，可以使字线电压与编程单元的位线电压相匹配。

5. 发明申请

US20120092923A1 READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY 有权
标题翻译：阅读配置管理相位变化记忆
公开(公告)号：US20120092923A1
公开(公告)日：2012-04-19
申请号：US12905754
申请日：2010-10-15
申请人： Ferdinando Bedeschi , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Roberto Gastaldi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2211/5634 , G11C2213/54
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
摘要翻译：本文公开的主题涉及存储器件，更具体地涉及写入相变存储器的性能。

6. 发明授权

US08149616B2 Method for multilevel programming of phase change memory cells using adaptive reset pulses 有权
标题翻译：使用自适应复位脉冲对相变存储单元进行多电平编程的方法
公开(公告)号：US08149616B2
公开(公告)日：2012-04-03
申请号：US12780580
申请日：2010-05-14
申请人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
发明人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0092
摘要： A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.
摘要翻译：用于编程多电平PCM单元的方法设想：通过施加一个或多个复位脉冲，在PCM单元的存储元件中形成非晶相变材料的非晶区域; 以及通过施加一个或多个设定脉冲，形成所述PCM单元的编程状态的导电路径的大小和与其相关联的输出电量，并通过所述值来控制所述晶体相变材料的导电路径通过所述非晶区域的复位脉冲和设定脉冲。形成非晶区域的步骤设想在编程操作期间自适应地和迭代地确定针对PCM单元的电气和/或物理特性优化的复位脉冲的值，特别是确定复位脉冲的最小振幅值，这允许编程期望的编程状态和输出电量的期望值。

7. 发明授权

US08018763B2 Adaptive wordline programming bias of a phase change memory 有权
公开(公告)号：US08018763B2
公开(公告)日：2011-09-13
申请号：US12963717
申请日：2010-12-09
申请人： Richard E. Fackenthal , Ferdinando Bedeschi , Meenatchi Jagasivamani , Ravi Annavajjhala , Enzo M. Donze
发明人： Richard E. Fackenthal , Ferdinando Bedeschi , Meenatchi Jagasivamani , Ravi Annavajjhala , Enzo M. Donze
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , Y10S977/754
摘要： The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

8. 发明授权

US07936584B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US07936584B2
公开(公告)日：2011-05-03
申请号：US12354425
申请日：2009-01-15
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/06
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

9. 发明授权

US07869269B2 Phase-change memory device with error correction capability 有权
标题翻译：具有纠错能力的相变存储器件
公开(公告)号：US07869269B2
公开(公告)日：2011-01-11
申请号：US12209967
申请日：2008-09-12
申请人： Enzo Michele Donzè , Ferdinando Bedeschi , Meenatchi Jagasivamani
发明人： Enzo Michele Donzè , Ferdinando Bedeschi , Meenatchi Jagasivamani
IPC分类号： G11C11/00
CPC分类号： B01F7/04 , B01F7/00258 , B01F7/00425 , B01F13/06 , B01F2015/0221 , G06F11/1068 , G11C13/02
摘要： A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.
摘要翻译：相变存储器件包括用于存储数据位的多个数据PCM单元; 用于有选择地寻址数据PCM单元的数据解码电路; 以及用于读取和编程所选数据PCM单元的数据读/写电路。该设备还包括多个奇偶校验PCM单元，用于存储与存储在数据PCM单元中的数据比特相关联的奇偶校验位; 用于选择性地寻址奇偶校验PCM单元组的奇偶解码电路; 以及用于读取和编程所选奇偶校验PCM单元的奇偶读/写电路。

10. 发明申请

US20100165725A1 RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL 有权
标题翻译：相变存储单元的可靠设置操作
公开(公告)号：US20100165725A1
公开(公告)日：2010-07-01
申请号：US12623299
申请日：2009-11-20
申请人： Ferdinando Bedeschi
发明人： Ferdinando Bedeschi
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed.
摘要翻译：描述了相变存储器（PCM）装置和将数据写入PCM装置的方法。 PCM装置包括具有至少设置状态和复位状态的多相数据存储单元，该状态可以使用配置为加热数据存储单元的加热器来建立。存储器接口可以与被配置为将数据写入数据存储单元的加热器耦合，该数据由Set或Reset状态表示。写入复位脉冲用于将数据存储单元置于与读取值小于读取阈值的读取值对应的复位状态。使用作为写入复位脉冲的预定功能的写入设置脉冲将数据存储单元置于置位状态。 PCM设备可以包括允许每个数据存储单元存储两个或更多个位的信息的附加中间状态。可以描述和要求保护其他实施例。

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