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31. 发明授权

US5448083A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5448083A
公开(公告)日：1995-09-05
申请号：US261384
申请日：1994-06-15
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36 , H01L21/74
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面上形成与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

32. 发明授权

US5378920A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5378920A
公开(公告)日：1995-01-03
申请号：US85055
申请日：1993-07-02
申请人： Akio Nakagawa , Norio Yasuhara
发明人： Akio Nakagawa , Norio Yasuhara
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/402
摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region. A fifth semiconductor region having an impurity concentration lower than that of the second or fourth semiconductor region is formed on a bottom portion of the first semiconductor region. When a reverse bias is applied between the second and fourth semiconductor regions, a depletion layer extends vertically in the first semiconductor region and laterally in the fifth semiconductor region. The applied voltage is divided in both the directions and a high breakdown voltage can be obtained.
摘要翻译：高耐压电压半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一半导体区域，具有高于第一绝缘膜的杂质浓度的第一导电类型的第二半导体区域第一半导体区域，并且选择性地形成在第一半导体区域的表面部分上，第三半导体区域具有杂质浓度低于第二半导体区域的杂质浓度，并形成在第一半导体区域的表面部分上，以便邻近或在第二半导体区域附近形成杂质浓度高于第一半导体区域的第二导电类型的第四半导体区域，并且形成在第一半导体区域的表面部分上，以便在第三半导体区域的外部。在第一半导体区域的底部形成有杂质浓度低于第二或第四半导体区域的第五半导体区域。当在第二和第四半导体区域之间施加反向偏压时，耗尽层在第一半导体区域中垂直延伸并且在第五半导体区域中横向延伸。施加的电压在两个方向上被分割，并且可以获得高的击穿电压。

33. 发明授权

US5369734A Method for processing and displaying hidden-line graphic images 失效
标题翻译：处理和显示隐藏图形图像的方法
公开(公告)号：US5369734A
公开(公告)日：1994-11-29
申请号：US701084
申请日：1991-05-16
申请人： Yoshie Suzuki , Shin Nakamura , Akio Nakagawa
发明人： Yoshie Suzuki , Shin Nakamura , Akio Nakagawa
IPC分类号： G06T15/40 , G06F15/72
CPC分类号： G06T15/40
摘要： In a graphic display processing method, a surface to be displayed is regarded as an aggregation of rectangular meshes, a painting function of a graphic terminal is performed on mesh strips from the one farthest from a viewpoint to the one closest to the viewpoint, and the meshes are displayed and hidden-line processed to eliminate hidden-lines from the image. The twist state of each mesh and the twist between two adjacent meshes are determined. A plurality of twist-free meshes are painted as a group.
摘要翻译：在图形显示处理方法中，要显示的表面被认为是矩形网格的聚集，对从最靠近视点的网格条到最接近视点的网格条的网格条进行图形终端的绘画功能，网格被显示并进行隐藏处理，以消除图像中的隐藏线。确定每个网格的扭曲状态和两个相邻网格之间的扭曲。多个无捻网格被画成一组。

34. 发明授权

US5343067A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5343067A
公开(公告)日：1994-08-30
申请号：US829214
申请日：1992-01-31
申请人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
发明人： Akio Nakagawa , Norio Yasuhara , Tomoko Matsudai
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/404 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286
摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.
摘要翻译：一种高耐压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上的高电阻半导体层，形成在高电阻半导体层中的隔离区，形成在高电阻半导体中的元件区在横向方向上被隔离区域隔离的层，形成在元件区域的中心表面部分中的第一导电类型的第一低电阻区域和形成在元件区域的中心表面部分中的第二导电类型的第二低电阻区域，元素区域。元件区域中的杂质的剂量被设定为使得当在第一和第二低电阻区域之间施加电压时，第一低电阻区域和第二低电阻区域之间的元件区域的一部分被完全耗尽。

35. 发明授权

US5272365A Silicon transistor device with silicon-germanium electron gas hetero structure channel 失效
标题翻译：硅晶体管器件采用硅锗电子气异质结构通道
公开(公告)号：US5272365A
公开(公告)日：1993-12-21
申请号：US887667
申请日：1992-05-26
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/165 , H01L29/737 , H01L29/778 , H01L29/78 , H01L29/161 , H01L27/14 , H01L29/205 , H01L29/225
CPC分类号： H01L29/66477 , H01L21/26506 , H01L29/165 , H01L29/7378 , H01L29/7781 , H01L29/7782 , H01L29/78
摘要： A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of the substrate. A gate electrode of polycrystalline silicon is disposed above the substrate, and is electrically insulated from the substrate by a gate insulation layer made of thermal silicon oxide thin film. A silicon germanium layer is laterally provided in a preselected substrate surface section positioned between the source and drain layers. This layer partially overlaps the source and drain layers at both of its end portions, and is thus electrically in contact with these layers. The silicon germanium layer acts as a channel of the transistor.
摘要翻译：具有异质结构的金属氧化物半导体场效应晶体管具有硅衬底。与衬底不同的导电类型的重掺杂源极和漏极层在衬底的表面部分彼此间隔开。多晶硅的栅电极设置在基板上方，并且通过由热氧化硅薄膜制成的栅极绝缘层与基板电绝缘。横向地设置在位于源层和漏层之间的预选的衬底表面部分中的硅锗层。该层在其两端部与源极层和漏极层部分重叠，因此与这些层电接触。硅锗层用作晶体管的沟道。

36. 发明授权

US5133773A Teaching playback swing-phase-controlled above-knee prosthesis 失效
标题翻译：教学回放摆动相控膝上假体
公开(公告)号：US5133773A
公开(公告)日：1992-07-28
申请号：US729682
申请日：1991-07-15
申请人： Seishi Sawamura , Sakuya Nakajima , Kunio Amemori , Hidehisa Oku , Akio Nakagawa , Ichiro Kitayama , Hiromu Matsuda , Katsuhiko Yoshida , Masaru Takeda , Toshio Nakane , Shiro Horiguchi , Shigeru Yuki
发明人： Seishi Sawamura , Sakuya Nakajima , Kunio Amemori , Hidehisa Oku , Akio Nakagawa , Ichiro Kitayama , Hiromu Matsuda , Katsuhiko Yoshida , Masaru Takeda , Toshio Nakane , Shiro Horiguchi , Shigeru Yuki
IPC分类号： A61F2/64 , A61F2/68 , A61F2/70 , A61F2/74
CPC分类号： A61F2/68 , A61F2/64 , A61F2002/6818 , A61F2002/704 , A61F2002/747 , A61F2002/748
摘要： A teaching playback swing-phase-controlled above-knee prosthesis comprises a thigh frame, a leg frame, an air cylinder interconnecting the thigh and leg frames and provided with adjusting means for adjusting the degree of opening the valve of the air cylinder to a plurality of degrees respectively for a plurality of walking speeds selected during trial walking, a mode selecting switch having positions respectively for setting degrees of opening of the valve of the air cylinder in a teaching mode and for a playback mode in which one of the degrees of opening is selected according to an actual walking speed, an opening detector for detecting the degree of opening of the valve of the air cylinder, an opening storage device for storing a plurality of set degreess of opening of the valve of the air cylinder, a phase detector for detecing swing phases and stance phases, walking speed detector for detecting an actual walking speed, and control unit for adjusting the degree of opening of the valve of the air cylinder to one of the set degrees of opening corresponding to the actual walking speed. The teaching playback swing-phase-controlled-above-knee prothesis is capable of automatically controlling the speed of swing motion of the leg frame according to the actual walking speed of the prosthesis wearer.
摘要翻译：示教播放摆动相位控制的膝上假体包括大腿架，腿架，连接大腿和腿框架的气缸，并设置有用于将气缸的阀打开程度调节到多个的调节装置分别用于在试运行期间选择的多个步行速度的模式选择开关，具有分别用于在示教模式下设置气缸的开度的位置的模式选择开关以及其中一个开度根据实际行走速度选择，用于检测气缸的阀的开度的开度检测器，用于存储气缸的阀的多个设定开度的开放存储装置，相位检测器用于检测摆动相位和姿势相位，用于检测实际步行速度的步行速度检测器和用于调节v的开度的控制单元气瓶的一部分与设定的开度相对应的实际行走速度之一。教学回放摆动相位控制上膝盖假体能够根据假体佩戴者的实际步行速度自动控制腿部框架的摆动运动速度。

37. 发明授权

US4866315A Turn-on/off driving technique for insulated gate thyristor 失效
标题翻译：绝缘栅极晶闸管的开/关驱动技术
公开(公告)号：US4866315A
公开(公告)日：1989-09-12
申请号：US161095
申请日：1988-02-26
申请人： Tsuneo Ogura , Akio Nakagawa
发明人： Tsuneo Ogura , Akio Nakagawa
IPC分类号： H01L29/08 , H01L29/10 , H01L29/744 , H01L29/749 , H03K17/732
CPC分类号： H01L29/102 , H01L29/0834 , H01L29/744 , H01L29/749 , H03K17/732
摘要： A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and functioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application. At this time, charge carriers exhausted from the second emitter layer are allowed to flow into the first base layer through the channel region of the MOSFET, thereby suppressing the local concentration of the turn-off current in the thyristor.

38. 发明授权

US4821083A Thyristor drive system 失效
标题翻译：晶闸管驱动系统
公开(公告)号：US4821083A
公开(公告)日：1989-04-11
申请号：US101790
申请日：1987-09-28
申请人： Tsuneo Ogura , Katsuhiko Takigami , Akio Nakagawa , Tomokazu Domon
发明人： Tsuneo Ogura , Katsuhiko Takigami , Akio Nakagawa , Tomokazu Domon
IPC分类号： H01L29/08 , H01L29/744 , H03K17/00 , H03K17/732
CPC分类号： H01L29/0834 , H01L29/744 , H03K17/732 , H03K2217/0036
摘要： A gate turn-off thyristor drive system with low power loss when it is in the turn-off mode, is disclosed. A first turn-off pulse of a predetermined amplitude is applied to a first gate electrode. A second turn-off pulse is applied to a second gate electrode. An amplitude of the second turn-off pulse is smaller in absolute value than that of the first turn-off pulse. The fall time of the anode current at the time of turn-off is reduced, and the initial value of the tail current of the anode current is reduced. The power loss as the product of the anode voltage and the anode current is reduced.
摘要翻译：公开了一种在关闭模式时具有低功率损耗的栅极截止晶闸管驱动系统。将预定幅度的第一关断脉冲施加到第一栅电极。第二截止脉冲被施加到第二栅电极。第二截止脉冲的幅度的绝对值小于第一截止脉冲的幅度。在关断时的阳极电流的下降时间减少，阳极电流的尾电流的初始值减小。作为阳极电压和阳极电流的乘积的功率损耗减小。

39. 发明授权

US4672407A Conductivity modulated MOSFET 失效
标题翻译：电导率调制MOSFET
公开(公告)号：US4672407A
公开(公告)日：1987-06-09
申请号：US738188
申请日：1985-05-28
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.
摘要翻译：一种电导率调制MOSFET，具有第一导电类型的半导体衬底，形成在半导体衬底上并且具有高电阻的第二导电类型的半导体层，形成在半导体层中的第一导电类型的基极层，源极形成在基底层中的第二导电类型的层，形成在形成在沟道区上的栅极绝缘膜上的栅电极，沟道区形成在半导体层和源极层之间的基底层的表面中，欧姆接触源极层和基极层的源电极以及形成在半导体衬底的与半导体层相反的表面上的漏电极，其特征在于，导电调制MOSFET的饱和电流小于闭锁电流当预定的栅极电压施加到栅电极时。

40. 发明授权

US08972769B2 Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios 有权
标题翻译：数据处理装置和控制方法，用于根据计算出的频率响应时间比来控制时钟频率
公开(公告)号：US08972769B2
公开(公告)日：2015-03-03
申请号：US13011712
申请日：2011-01-21
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06F1/04 , G06F15/16 , G06F9/30 , G06F9/40 , G06F9/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
摘要翻译：数据处理装置包括：多个处理单元，适于根据输入的操作时钟处理数据; 以及控制单元，其适于在向所述多个处理单元提供公共频率的操作时钟时测量所述多个处理单元的响应时间，并且控制要提供给所述多个处理单元中的至少一个的所述操作时钟的频率多个处理单元，使得多个测量的响应时间变得更接近。

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