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    • 31. 发明授权
    • Low power variable delay circuit
    • 低功率可变延迟电路
    • US08278981B2
    • 2012-10-02
    • US12636901
    • 2009-12-14
    • Hae-Rang ChoiYong-Ju KimSung-Woo HanHee-Woong SongIc-Su OhHyung-Soo KimTae-Jin HwangJi-Wang LeeJae-Min JangChang-Kun Park
    • Hae-Rang ChoiYong-Ju KimSung-Woo HanHee-Woong SongIc-Su OhHyung-Soo KimTae-Jin HwangJi-Wang LeeJae-Min JangChang-Kun Park
    • H03L7/00
    • G11C19/28
    • A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
    • 可变延迟电路至少包括固定延迟单元,第一选择单元和可变延迟单元。 固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号,并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。 第一选择单元接收输入信号,第一延迟信号和第二延迟选择信号,并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。 可变延迟单元还接收表示第三延迟的第三延迟选择信号,并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。 第一个延迟是M个延迟单位的0或X倍。 第三延迟是从0到N个延迟单元中选择的延迟。