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31. 发明授权

US4616404A Method of making improved lateral polysilicon diode by treating plasma etched sidewalls to remove defects 失效
标题翻译：通过处理等离子体蚀刻侧壁来去除缺陷来制造改进的横向多晶硅二极管的方法
公开(公告)号：US4616404A
公开(公告)日：1986-10-14
申请号：US676684
申请日：1984-11-30
申请人： Scott W. Wang , Mammen Thomas , Wen C. Ko
发明人： Scott W. Wang , Mammen Thomas , Wen C. Ko
IPC分类号： H01L29/78 , H01L21/3215 , H01L21/331 , H01L29/04 , H01L29/73 , H01L29/861 , H01L21/265 , H01L21/425
CPC分类号： H01L29/04 , H01L21/32155 , H01L29/861 , Y10S148/01
摘要： An improved lateral polysilicon diode in an integrated circuit structure is disclosed. The diode is characterized by low reverse current leakage, a breakdown voltage of at least 5 volts, and low series resistance permitting high current flow before being limited by saturation. The polysilicon diode comprises a polysilicon substrate having a first zone sufficiently doped to provide a first semiconductor type and a second zone sufficiently doped to provide a second semiconductor type whereby the junction between the two zones forms a diode. The lateral edges of the diode are treated to remove defects to thereby inhibit current leakage around the edges of the lateral diode to lower the reverse current leakage of the diode.
摘要翻译：公开了一种集成电路结构中的改进的侧向多晶硅二极管。二极管的特征在于低反向电流泄漏，至少5伏的击穿电压，以及在受饱和限制之前允许高电流流动的低串联电阻。多晶硅二极管包括具有充分掺杂以提供第一半导体类型的第一区域和充分掺杂以提供第二半导体类型的第二区域的多晶硅衬底，由此两个区域之间的结形成二极管。对二极管的横向边缘进行处理以消除缺陷，从而抑制横向二极管边缘周围的电流泄漏，以降低二极管的反向电流泄漏。

32. 发明授权

US4468285A Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide 失效
标题翻译：具有改善二氧化硅选择性的单晶硅的等离子体蚀刻工艺
公开(公告)号：US4468285A
公开(公告)日：1984-08-28
申请号：US564951
申请日：1983-12-22
申请人： Atiye Bayman , Mammen Thomas
发明人： Atiye Bayman , Mammen Thomas
IPC分类号： H01L21/302 , H01L21/205 , H01L21/3065 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/3065
摘要： A plasma etching composition is set forth which comprises chlorine in an amount from about 40% to about 90%, a shape modifier species in an amount from about 10% to about 60%, and an etching selectivity enhancer in an amount sufficient to render the composition at least about 10 times as effective for etching a wafer as for etching a masking layer, the above percents being by mole. The composition is useful for plasma etching of a semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched in order to form a depression of a desired depth. This allows depressions of increased depth to be formed in wafers without increasing the thickness of the masking layer.
摘要翻译：提出了一种等离子体蚀刻组合物，其包含约40％至约90％的氯，约10％至约60％的形状改性剂种类和一种蚀刻选择性增强剂，其量足以使组合物对蚀刻掩模层的蚀刻晶片的至少约10倍有效，上述百分比是摩尔数。该组合物对于用具有开口的掩模层掩蔽的半导体晶片的等离子体蚀刻是有用的，暴露待蚀刻的晶片的一部分以形成期望深度的凹陷。这允许在晶片中形成增加深度的凹陷，而不增加掩模层的厚度。

33. 发明授权

US4456501A Process for dislocation-free slot isolations in device fabrication 失效
标题翻译：器件制造中无位错插槽隔离的过程
公开(公告)号：US4456501A
公开(公告)日：1984-06-26
申请号：US564813
申请日：1983-12-22
申请人： Atiye Bayman , Mammen Thomas
发明人： Atiye Bayman , Mammen Thomas
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/76 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/3065
摘要： A semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched to form a depression of a desired depth is etched via a first plasma etching step under high bias voltage-high energy conditions with a plasma which includes chlorine and a shape modifier species, e.g., argon, to a first depth which is less than the desired depth. Thereafter, the depression is treated by a second plasma etching step under low bias voltage-low energy plasma etching conditions with a plasma which includes chlorine and is substantially free of the shape modifier species. A wet chemical etch follows to remove damaged silicon and impurities. The resulting depression has relatively straight walls and is relatively free of cusps and apexes. The depression is formed quickly and has a desired shape while only a minimal amount of damage and impurities are introduced into the wafer.
摘要翻译：在具有等离子体的高偏压 - 高能条件下经由第一等离子体蚀刻步骤蚀刻半导体晶片，该掩模层具有通过其露出的开口的掩模层，暴露待蚀刻的晶片的一部分以形成所需深度的凹陷，其包括氯和形状调节剂物质，例如氩，至少于所需深度的第一深度。此后，通过第二等离子体蚀刻步骤，在包括氯的等离子体的低偏压 - 低能等离子体蚀刻条件下处理凹陷，并且基本上不含形状修饰物种。遵循湿化学蚀刻去除损坏的硅和杂质。所得到的凹陷具有相对直的壁并且相对没有尖和顶点。凹陷快速形成并且具有期望的形状，同时仅将最少量的损伤和杂质引入晶片。

34. 发明申请

US20160378708A1 PCI Express to PCI Express based Low Latency Interconnect Scheme for Clustering Systems 审中-公开
标题翻译：用于集群系统的PCI Express到基于PCI Express的低延迟互连方案
公开(公告)号：US20160378708A1
公开(公告)日：2016-12-29
申请号：US15175800
申请日：2016-06-07
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4282 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , H04L49/40
摘要： PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
摘要翻译： PCI Express是一种总线或I / O互连标准，用于计算机或嵌入式系统内部，可实现更快的数据传输到外围设备。该标准仍在不断发展，但已经达到了一定程度的稳定性，使其他应用程序可以使用PCIE作为基础来实现。一种基于PCIE的互连方案，可实现多个支持PCIE的系统之间的交换和互连，每个PCIE系统都具有自己的PCIE根系，因此PCIE架构的可扩展性可以应用于连接系统之间的数据传输以形成系统集群。提出。这些连接的系统可以是任何计算，控制，存储或嵌入式系统。互连的可扩展性将允许集群在系统变得必要时增加带宽，而不改变到不同的连接体系结构。

35. 发明申请

US20150381501A1 Method for congestion avoidance 审中-公开
标题翻译：避免拥塞的方法
公开(公告)号：US20150381501A1
公开(公告)日：2015-12-31
申请号：US14120845
申请日：2014-07-01
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/851 , H04L12/947 , H04L12/803
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.
摘要翻译：数据链路帧或网络分组包含报头中的协议信息，并且可选地包含帧或分组的尾部。我们提出了一种方法，其中在另一个数据链路帧中单独传输与帧或分组相对应的协议信息的一部分或全部。 “单独发送的协议信息”被称为STPI。 STPI包含足够的协议信息来标识下一跳节点或端口。 STPI可以避免网络拥塞，提高链路效率。优选地，将存在对应于每个STPI的一个数据链路帧或网络分组，其包含数据和协议信息的其余部分，并且该帧/分组被称为DFoNP。 STPI和DFoNP的创建由帧或数据包的发起者完成，例如操作系统。

36. 发明申请

US20080043737A1 Creation and transmission of part of protocol information corresponding to network packets or datalink frames separately 有权
标题翻译：分别与网络数据包或数据链路帧对应的协议信息的一部分的创建和传输
公开(公告)号：US20080043737A1
公开(公告)日：2008-02-21
申请号：US11505788
申请日：2006-08-18
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/56
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.
摘要翻译：数据链路帧或网络分组包含报头中的协议信息，并且可选地包含帧或分组的尾部。我们提出了一种方法，其中在另一个数据链路帧中单独传送与帧或分组相对应的协议信息的一部分或全部。 “单独发送的协议信息”被称为STPI。 STPI包含足够的协议信息来标识下一跳节点或端口。 STPI可以避免网络拥塞，提高链路效率。优选地，将存在对应于每个STPI的一个数据链路帧或网络分组，其包含数据和协议信息的其余部分，并且该帧/分组被称为DFoNP。 STPI和DFoNP的创建由帧或数据包的发起者完成，例如操作系统。

37. 发明授权

US07277437B1 Packet classification method 有权
标题翻译：分组分类方法
公开(公告)号：US07277437B1
公开(公告)日：2007-10-02
申请号：US10153137
申请日：2002-05-20
申请人： Neil Mammen , Mammen Thomas , Sanjay Agarwal , M. Varghese Ninan
发明人： Neil Mammen , Mammen Thomas , Sanjay Agarwal , M. Varghese Ninan
IPC分类号： H04L12/26 , H04L12/56 , H04J1/16 , G08C15/00 , G06F11/00
CPC分类号： H04L45/00 , H04L45/60 , H04L45/7453
摘要： According to one embodiment, a network hardware machine is disclosed. The network hardware machine includes a central processing unit (CPU) that processes data packets received at the network hardware machine, and a classifier, coupled to the CPU, that classifies the packets prior to the packets being received at the CPU.
摘要翻译：根据一个实施例，公开了一种网络硬件机器。网络硬件机器包括处理在网络硬件机器处接收的数据分组的中央处理单元（CPU），以及耦合到CPU的分类器，其在CPU接收到分组之前对分组进行分类。

38. 发明授权

US07227786B1 Location-specific NAND (LS NAND) memory technology and cells 有权
标题翻译：位置特定NAND（LS NAND）存储器技术和单元
公开(公告)号：US07227786B1
公开(公告)日：2007-06-05
申请号：US11174333
申请日：2005-07-05
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/12 , G11C16/16 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Buckyball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Buckyball Oxide layer is used as the storage element.The problem of location-specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.
摘要翻译：使用能够定位特定（LS）电荷存储的氮化物层或硅结节层，可以轻松地垂直缩放和实现NOR和NAND NVM阵列和技术。如果电荷存储在氮化物存储层中的陷阱中，则使用氧化氮氮氧化物作为存储元件，并且如果电荷存储在离散硅结节或碳黑球层的潜在阱中，则氧化物硅结节氧化物存储元素或氧化物巴克球氧化物层用作存储元件。位置特定的NAND存储器的问题是无法用可重复的结果擦除单元。一种新颖的擦除方法，隧道枪（TG）方法，其产生用于LS存储元件和典型NAND单元的一致擦除的空穴，该NAND存储元件通过所公开的方法擦除并由Fouler-Nordheim（FN）隧道或低电流热电子 LCHE）方法。

39. 发明授权

US5675161A Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications 失效
标题翻译：通道加速隧道电子单元，具有选择区域，用于高密度低功率应用
公开(公告)号：US5675161A
公开(公告)日：1997-10-07
申请号：US411533
申请日：1995-03-28
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , G11C11/34 , H01L29/792
CPC分类号： H01L29/42324 , H01L27/115 , H01L29/7885
摘要： Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area. By separating the portion of the gate on the side wall from that over the surface, along a continuous channel between the source and drain, independently operating storage region and a select/accelerating region are formed along the same channel. This structure allows independent voltages to be applied to the storage gate and the accelerating gate. These CATE cells allow low supply current operation. Since all the operations are low current operations, efficient pumps can be used on chip to provide the required high voltages where needed.
摘要翻译：公开了能够电适应写入和擦除的改进的非易失性存储单元，适用于高密度低电压应用。写入单元是通过使用用于编程存储器的通道加速载波隧道（CACT）方法（1994年3月11日提交的专利申请号08 / 209,787），并且擦除是通过隧穿穿过薄氧化物区域。公开了两个结构实施例。第一实施例，沟槽加速隧道电子单元（Tr-CATE）和第二实施例沟槽壁加速隧道电子单元（Tw-CATE）都利用通道的分离区域进行写入和擦除，因此提供操作可靠性高。公开的单元使用垂直步进蚀刻来形成通道的一部分以加速载流子，并且还用作选择栅极而不增加单元面积。通过沿着源极和漏极之间的连续沟道将侧壁上的栅极部分与表面上的栅极分离，沿着相同的沟道形成独立操作的存储区域和选择/加速区域。这种结构允许将独立电压施加到存储栅极和加速栅极。这些CATE电池允许低电流工作。由于所有操作都是低电流操作，因此可以在芯片上使用高效的泵来在需要时提供所需的高电压。

40. 发明授权

US5502315A Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
标题翻译：具有PECVD非晶硅元件的电可编程互连结构
公开(公告)号：US5502315A
公开(公告)日：1996-03-26
申请号：US161504
申请日：1993-12-02
申请人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
发明人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
IPC分类号： H01L23/525 , H02L27/02
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
摘要翻译：在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

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