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31. 发明授权

US08238155B2 Multilevel memory cell operation 有权
标题翻译：多层存储单元操作
公开(公告)号：US08238155B2
公开(公告)日：2012-08-07
申请号：US12703540
申请日：2010-02-10
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell.
摘要翻译：本公开的一个或多个实施例提供了用于操作非易失性多电平存储器单元的方法，装置和系统。一个方法实施例包括将存储器单元编程为多个不同阈值电压（Vt）电平之一，每个电平对应于编程状态。该方法包括将参考单元编程至至少与不同Vt电平数量的最高Vt电平一样大的Vt电平，对参考单元执行读取操作，以及确定用于确定特定值的读取参考电压的数量基于对参考单元执行的读取操作，存储器单元的编程状态。

32. 发明申请

US20120140569A1 MEMORY CELL OPERATION 有权
标题翻译：记忆体操作
公开(公告)号：US20120140569A1
公开(公告)日：2012-06-07
申请号：US13372669
申请日：2012-02-14
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/14
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

33. 发明申请

US20120069680A1 NAND WITH BACK BIASED OPERATION 有权
标题翻译： NAND带反向偏移操作
公开(公告)号：US20120069680A1
公开(公告)日：2012-03-22
申请号：US13308020
申请日：2011-11-30
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/10 , G11C16/14 , G11C16/26
CPC分类号： G11C16/0483 , G11C16/10
摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts
摘要翻译：公开了编程，读取和擦除存储器单元的方法。在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏零伏

34. 发明申请

US20110216600A1 DRAIN SELECT GATE VOLTAGE MANAGEMENT 有权
标题翻译：排水门电压管理
公开(公告)号：US20110216600A1
公开(公告)日：2011-09-08
申请号：US12715530
申请日：2010-03-02
申请人： Akira Goda , Pranav Kalavade , Doyle Rivers
发明人： Akira Goda , Pranav Kalavade , Doyle Rivers
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C16/04 , G11C16/0433
摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值在第二编程时间段的后续部分中，栅极电压与第一值不同。漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。公开了附加装置，系统和方法。

35. 发明申请

US20110199827A1 MEMORY ARRAY HAVING MEMORY CELLS COUPLED BETWEEN A PROGRAMMABLE DRAIN SELECT GATE AND A NON-PROGRAMMABLE SOURCE SELECT GATE 有权
标题翻译：具有可编程排水选择门和不可编程源选择门之间的记忆细胞的记忆阵列
公开(公告)号：US20110199827A1
公开(公告)日：2011-08-18
申请号：US12707162
申请日：2010-02-17
申请人： Giuseppina Puzzilli , Andrew Bicksler , Akira Goda
发明人： Giuseppina Puzzilli , Andrew Bicksler , Akira Goda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483
摘要： Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.
摘要翻译：记忆及其记忆阵列被公开。一个这样的存储器阵列具有一串串联耦合的存储器单元，串联耦合到串联耦合存储器单元串的第一端的非可编程选择栅极，以及串联耦合到第二端的可编程选择栅极串联的存储单元串。

36. 发明申请

US20110194352A1 PROGRAMMING METHODS AND MEMORIES 有权
标题翻译：编程方法和记忆
公开(公告)号：US20110194352A1
公开(公告)日：2011-08-11
申请号：US12702948
申请日：2010-02-09
申请人： Yijie Zhao , Akira Goda
发明人： Yijie Zhao , Akira Goda
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.
摘要翻译：公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。

37. 发明申请

US20110188312A1 METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS 有权
标题翻译：用于参考细胞的编程监视器的存储器细胞损伤的方法
公开(公告)号：US20110188312A1
公开(公告)日：2011-08-04
申请号：US13082965
申请日：2011-04-08
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/04 , G11C16/28
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

38. 发明申请

US20110164455A1 MEMORY CELL OPERATION 有权
标题翻译：记忆体操作
公开(公告)号：US20110164455A1
公开(公告)日：2011-07-07
申请号：US13049464
申请日：2011-03-16
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

39. 发明授权

US07883964B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07883964B2
公开(公告)日：2011-02-08
申请号：US12181978
申请日：2008-07-29
申请人： Akira Goda , Hiroyuki Nitta
发明人： Akira Goda , Hiroyuki Nitta
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , G11C16/0416 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526
摘要： A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.
摘要翻译：非易失性半导体存储器包括：器件区域和器件隔离区域，其具有沿第一方向延伸的条纹形式的图案，并且在垂直于第一方向的第二方向上以第一间距交替地并且顺序地设置方向; 以及由第一导电材料制成的接触件，其连接到器件区域并沿第二方向以第一间距设置。在第二方向的横截面上，触点的底部宽度比触点的顶部宽度长，并且底部宽度比器件区域的宽度长。

40. 发明申请

US20100091544A1 COUPLINGS WITHIN MEMORY DEVICES 有权
标题翻译：存储器件中的耦合
公开(公告)号：US20100091544A1
公开(公告)日：2010-04-15
申请号：US12637163
申请日：2009-12-14
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C7/02 , G11C7/1036 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.
摘要翻译：存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

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