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31. 发明授权

US07675326B1 Dynamically-adjustable differential output drivers 失效
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07675326B1
公开(公告)日：2010-03-09
申请号：US12163709
申请日：2008-06-27
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

32. 发明授权

US07039787B1 Byte alignment circuitry 失效
标题翻译：字节对齐电路
公开(公告)号：US07039787B1
公开(公告)日：2006-05-02
申请号：US10984684
申请日：2004-11-09
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/4018 , H04J3/0608
摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.
摘要翻译：用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。如果字节对齐电路随后检测到提示可能需要新的或改变的字节对齐的信息，则输出第二状态信号。然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

33. 发明授权

US06867616B1 Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
标题翻译：具有双用途锁相环电路的可编程逻辑器件串行接口
公开(公告)号：US06867616B1
公开(公告)日：2005-03-15
申请号：US10455773
申请日：2003-06-04
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H03K19/173 , H03D3/24
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
摘要翻译：在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

34. 发明授权

US08363770B1 Oversampling with programmable pointer adjustment 有权
标题翻译：可编程指针调整过采样
公开(公告)号：US08363770B1
公开(公告)日：2013-01-29
申请号：US11555570
申请日：2006-11-01
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H04L12/50
CPC分类号： H04L7/0338 , H04L7/0331
摘要： Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.
摘要翻译：系统，方法和电路在存在噪声和/或抖动的情况下从过采样数据流中提取数据。指针决定提取过采样数据流的哪些数据样本。在数据转换之后发生的一些指针基于先前指针的位置而定位，而不是使用在对齐期间发生的数据转换点。诸如指针与数据转换对齐频率的频率以及在对准期间的最大调整量的设置可以是可编程的。

35. 发明授权

US07940814B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07940814B2
公开(公告)日：2011-05-10
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04J3/04
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

36. 发明申请

US20110090101A1 DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS 有权
标题翻译：数字相位锁定环路和方法
公开(公告)号：US20110090101A1
公开(公告)日：2011-04-21
申请号：US12974949
申请日：2010-12-21
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03L7/089 , H03L2207/50 , H04L7/0008 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。出于同样的原因，发射侧可能会使用过量传输或过采样。

37. 发明授权

US07698482B2 Multiple data rates in integrated circuit device serial interface 有权
标题翻译：集成电路设备串行接口中的多种数据速率
公开(公告)号：US07698482B2
公开(公告)日：2010-04-13
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
发明人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

38. 外观设计

USD338104S Carrying case for a computer 失效
公开(公告)号：USD338104S
公开(公告)日：1993-08-10
申请号：US774287
申请日：1991-10-10
申请人： Chong H. Lee
设计人： Chong H. Lee

39. 发明授权

US08787352B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US08787352B2
公开(公告)日：2014-07-22
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L12/28 , H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

40. 发明授权

US08098087B1 Method and apparatus for standby voltage offset cancellation 失效
标题翻译：待机电压失调消除的方法和装置
公开(公告)号：US08098087B1
公开(公告)日：2012-01-17
申请号：US11682282
申请日：2007-03-05
申请人： John Dung-Ngoc Lam , Arch Zaliznyak , Wilson Wong , Tin H. Lai , Chong H. Lee , Sergey Shumarayev
发明人： John Dung-Ngoc Lam , Arch Zaliznyak , Wilson Wong , Tin H. Lai , Chong H. Lee , Sergey Shumarayev
IPC分类号： H03K5/08
CPC分类号： H04L25/03878 , H03K5/249
摘要： A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.
摘要翻译：提供了一种方法和装置，用于在接收器通道内的比较器的输入处的待机电压偏移消除。第一比较器输入和第二比较器输入中的每一个与输入信号隔离，使得第一和第二比较器输入中的每一个达到相应的待机电压电平。在第一和第二比较器输入之一上的电压电平递增地改变，同时监视比较器的输出信号。在检测到比较器的输出信号中的状态转变时，一个比较器输入端的电压电平的增量变化在最终电压电平设置下停止。最后的电压电平设置存储在计算机存储器中，用于参考在一个比较器输入处的电压电平的设置，以便补偿在比较器的输入处的待机电压偏移。

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