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1. 发明公开

US20240259006A1 Semiconductor Chip With an Integrated Circuit 审中-公开
公开(公告)号：US20240259006A1
公开(公告)日：2024-08-01
申请号：US18423973
申请日：2024-01-26
申请人： TDK-Micronas GmbH
发明人： David Muthers
IPC分类号： H03K5/24 , H02M3/07
CPC分类号： H03K5/249 , H02M3/07
摘要： A semiconductor chip with an integrated circuit has supply voltage connectors and an output stage with an output for releasing an output signal. The output is connected via a drain-source line of a first self-closing insulated-gate field-effect transistor to an output connection for the output signal. The semiconductor chip has a clock signal generator fed from the supply voltage connections, its clock signal output is connected galvanically decoupled to an input voltage connection of a charge pump. A first output voltage connection of the charge pump is connected to the gate, and a second output voltage connection is connected to the bulk of the insulated-gate field-effect transistor. The output voltage connections are also connected to one another by means of a discharge path.

2. 发明公开

US20240213963A1 PULL-UP VOLTAGE DETECTION CIRCUIT AND PULL-UP VOLTAGE DETECTION METHOD 审中-公开
公开(公告)号：US20240213963A1
公开(公告)日：2024-06-27
申请号：US18539356
申请日：2023-12-14
申请人： Richtek Technology Corporation
发明人： Chien-Tzu Ko , Jiun-Jang Lin , Yan-Jhen Huang , Jhen-Yu Li
IPC分类号： H03K3/0233 , H03K5/08 , H03K5/24 , H03K19/17728
CPC分类号： H03K3/02332 , H03K5/082 , H03K5/249 , H03K19/17728
摘要： A pull-up voltage detection circuit is for use in a serial bus. The serial bus includes a communication signal. During a communication interval, the communication signal is toggled based on a pull-up voltage for communicating on the serial bus via open-drain scheme. The pull-up voltage detection circuit includes: at least one comparator circuit for comparing the communication signal or a divided voltage thereof with at least one reference voltage in a detection procedure, so as to generate at least one comparison result; and a selector circuit for selecting one of plural predetermined voltages according to the at least one comparison result. The selected predetermined voltage serves as a logic threshold voltage corresponding to the pull-up voltage. In the communication interval, the logic state of the communication signal is determined by comparing the communication signal and the logic threshold voltage for communicating on the serial bus.

3. 发明授权

US11996841B2 Comparator circuit and driver 有权
公开(公告)号：US11996841B2
公开(公告)日：2024-05-28
申请号：US17955190
申请日：2022-09-28
申请人： JVCKENWOOD Corporation
发明人： Marta Dinata Anwar
IPC分类号： H03K19/00 , G09G3/20 , H03K3/012 , H03K5/24 , H03K17/687
CPC分类号： H03K19/0013 , G09G3/20 , H03K3/012 , H03K5/249 , H03K17/687 , G09G2310/0286 , G09G2330/021
摘要： A comparator circuit according to this embodiment includes: a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit configured to hold a data of a data input terminal based on a comparator clock signal and configured to output an enable signal for stopping an operation of the comparator element; and an internal signal generation circuit configured to output an internal signal to the data input terminal based on the matching signal and an output signal output from the flip-flop circuit.

4. 发明公开

US20240007088A1 CLOCK DISTRIBUTION DEVICE, AND SIGNAL PROCESSING DEVICE AND IMAGE DISPLAY APPARATUS INCLUDING SAME 审中-公开
公开(公告)号：US20240007088A1
公开(公告)日：2024-01-04
申请号：US18038334
申请日：2021-11-19
申请人： LG ELECTRONICS INC.
发明人： Mikko LAPINLAHTI , Klaus JOKINEN
IPC分类号： H03K3/037 , H03K5/24 , H03K5/26
CPC分类号： H03K3/037 , H03K5/249 , H03K5/26
摘要： The present disclosure relates to a clock distribution device, and a signal processing device and an image display apparatus including the same. The clock distribution device according to an embodiment of the present disclosure includes: a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels; and a flip-flop configured to receive an inverted signal in which the second pulse signal is inverted, wherein an output clock signal is output based on an output signal of the latch, an input clock signal, and an output signal of the flip-flop. Accordingly, the input clock signal may be simply distributed.

5. 发明授权

US11799461B1 Memory device and slew rate detector 有权
公开(公告)号：US11799461B1
公开(公告)日：2023-10-24
申请号：US18077172
申请日：2022-12-07
申请人： Winbond Electronics Corp.
发明人： Yen-Yu Chou
IPC分类号： H03K5/00 , H03K5/12 , H03K19/20 , H03K5/24 , H03K5/04 , H03K5/1534
CPC分类号： H03K5/12 , H03K5/04 , H03K5/1534 , H03K5/249 , H03K19/20
摘要： A memory device and a slew rate detector are provided. The slew rate detector includes a clock signal generator, a pulse signal generator, a plurality of sampling comparators, and a detection result generator. The clock signal generator multiplies a frequency of a base clock signal to generate clock signals. The pulse signal generator generates first pulse signals and second pulse signals according to the clock signals. Each of the sampling comparators samples each of transmission signals to generate a reference signal according to the first pulse signals, and samples each of the transmission signals to generate a comparison signal according to the second pulse signals. The sampling comparators compare the reference signals with the comparison signals to generate comparison results. The detection result generator performs an operation on the comparison results to generate detection results.

6. 发明申请

US20180198440A1 Voltage Comparator Circuit Including a Plurality of Voltage Controlled Delay Lines 审中-公开
公开(公告)号：US20180198440A1
公开(公告)日：2018-07-12
申请号：US15403631
申请日：2017-01-11
申请人： STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
发明人： Caixin Zhuang
IPC分类号： H03K5/24 , H03K3/037
CPC分类号： H03K5/2481 , H03K3/037 , H03K5/249 , H03K2005/00019 , H03K2005/00045
摘要： An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.

7. 发明申请

US20180115319A1 COMPARATOR, CIRCUIT DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, AND VEHICLE 审中-公开
公开(公告)号：US20180115319A1
公开(公告)日：2018-04-26
申请号：US15848269
申请日：2017-12-20
申请人： Seiko Epson Corporation
发明人： Hideo HANEDA
IPC分类号： H03M1/50 , H03K5/24 , H03M1/12 , H03M1/46 , H03F3/45 , H03K9/08
CPC分类号： H03M1/50 , H03F3/45475 , H03K5/249 , H03K9/08 , H03M1/1245 , H03M1/46 , H03M1/56
摘要： A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first primary conductivity type transistor of which current is controlled based on a first input signal, a first secondary conductivity type transistor of which current is controlled based on a second input signal, and a first delay buffer provided between the transistors. A second delay unit includes a second primary conductivity type transistor of which current is controlled based on a second input signal, a second secondary conductivity type transistor of which current is controlled based on a first input signal, and a second delay buffer provided between the transistors.

8. 发明授权

US09941872B2 Self resetting latch 有权
公开(公告)号：US09941872B2
公开(公告)日：2018-04-10
申请号：US15358617
申请日：2016-11-22
申请人： Marvell International Ltd.
发明人： Sasan Cyrusian
IPC分类号： H03K3/02 , H03K5/24 , H03K3/356 , H03M9/00 , H03M1/12
CPC分类号： H03K5/249 , H03K3/356113 , H03K5/24 , H03M1/12 , H03M1/124 , H03M9/00
摘要： An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.

9. 发明申请

US20170302258A1 COMPARATOR 审中-公开
公开(公告)号：US20170302258A1
公开(公告)日：2017-10-19
申请号：US15515623
申请日：2015-10-01
申请人： PRAGMATIC PRINTING LTD
发明人： JOAO DE OLIVEIRA
IPC分类号： H03K5/24
CPC分类号： H03K5/2481 , H03K5/249 , H03K19/09432
摘要： A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e−) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e−) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal.

10. 发明授权

US09755655B1 Dynamic quantizers having multiple reset levels 有权
公开(公告)号：US09755655B1
公开(公告)日：2017-09-05
申请号：US15453707
申请日：2017-03-08
申请人： Xilinx, Inc.
发明人： James G. Hudner
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03K5/249
摘要： Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature (“PVT”) and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering the voltage supply to the reset devices. The input referred RMS noise and offset voltage of the circuit can be improved (reduced) by raising the voltage supply to the reset devices. Similarly, increases in Vcm due to process and voltage scaling can be mitigated by raising the voltage supply to the reset devices. Control systems are also provided herein to control the voltage supply to the reset devices to accomplish these and other objectives.

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