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1. 发明申请

US20130181179A1 RACKABLE FENCING OF COMPONENTS OPTIMIZED FOR PREASSEMBLY SHIPPING 有权
标题翻译：组合优化用于预配运费
公开(公告)号：US20130181179A1
公开(公告)日：2013-07-18
申请号：US13351927
申请日：2012-01-17
申请人： Duane E. Langenwalter , Ning Xue
发明人： Duane E. Langenwalter , Ning Xue
IPC分类号： E04H17/16
CPC分类号： E04H17/1426
摘要： A rackable fence with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.
摘要翻译：带有轨道，支架托架和多个支架的可机架围栏。导轨限定了刚性的倒U形横截面。支架载体包括位于轨道内部并延伸穿过轨道内部的顶部跨距。支杆可枢转地附接到支架托架并且能够朝向轨道枢转。

2. 发明授权

US08488729B1 Deskew across high speed data lanes 有权
标题翻译：高速数据通道的偏斜校正
公开(公告)号：US08488729B1
公开(公告)日：2013-07-16
申请号：US12879706
申请日：2010-09-10
申请人： David W. Mendel , Brent A. Fairbanks , Ning Xue
发明人： David W. Mendel , Brent A. Fairbanks , Ning Xue
IPC分类号： H04L7/00
CPC分类号： H04L25/14
摘要： Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit (“IC”) is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned. If not, then data in a lane for which the training pattern ends earliest is delayed by an amount corresponding to the length of one or more cycles of the training pattern.
摘要翻译：公开了用于对准跨越多个车道的高速数据的方法和结构。在一个实施例中，提供了一种方法和集成电路（“IC”），用于在数据解扰之前跨多个数据通道接收和对准加扰的训练数据。在一些实现中，已知的加扰训练模式在每个通道中是不同的，并且对齐包括将每个通道中的输入训练数据与每个通道中的不同已知加扰训练模式进行比较。在一些实施方式中，在扰频数据对准然后被解扰后，根据已知的未加扰训练模式进行检查，以确保加扰的训练数据的对准是正确的。在替代实施例中，在对齐数据之前对数据进行解扰，但是对偏移校正电路输出进行监视以确定训练模式是否在跨越正在对准的多个通道的同一时间结束。如果不是，则训练模式最早结束的车道中的数据被延迟与训练模式的一个或多个周期的长度对应的量。

3. 发明授权

US07672789B2 Least-Square Deconvolution (LSD): a method to resolve DNA mixtures 有权
标题翻译：最小二乘解卷积（LSD）：一种解决DNA混合物的方法
公开(公告)号：US07672789B2
公开(公告)日：2010-03-02
申请号：US11413183
申请日：2006-04-28
申请人： Tse-Wei Wang , Ning Xue , John D Birdwell , Mark Rader , John Flaherty
发明人： Tse-Wei Wang , Ning Xue , John D Birdwell , Mark Rader , John Flaherty
IPC分类号： G06F7/00
CPC分类号： G06F19/18 , G06F19/22 , G06F19/24 , Y10S707/99943
摘要： Least Square Deconvolution (LSD) uses quantitative allele peak area derived from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.
摘要翻译：最小二乘解卷积（LSD）使用从含有多个贡献者的DNA的样品衍生的定量等位基因峰面积来解决每个贡献者的最佳拟合基因型。该分辨率基于找到每个轨迹处的质量比系数的最小二乘拟合最接近定量等位基因峰数据。可以汇集来自每个基因座的一致的顶级质量比组合，以在可用基因座的子集处形成至少一个复合DNA谱。排名最高的DNA谱可用于检查疑似病例的轮廓，或用于在DNA数据库中搜索匹配的分布。

4. 发明授权

US07642812B1 Distribution and synchronization of a divided clock signal 失效
标题翻译：分配和同步分频时钟信号
公开(公告)号：US07642812B1
公开(公告)日：2010-01-05
申请号：US11895594
申请日：2007-08-24
申请人： Ning Xue , Philip Clarke , Joseph Huang , Yan Chong
发明人： Ning Xue , Philip Clarke , Joseph Huang , Yan Chong
IPC分类号： H03K21/00 , H03B19/00
CPC分类号： H03K23/54 , G06F1/06 , G06F1/10
摘要： Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.
摘要翻译：公开了用于在电子设备中分配和同步分频时钟信号的方法和电路。在一个实施例的一个方面中，一系列寄存器分配分频时钟信号，并且该系列寄存器由全速时钟信号计时，分频时钟信号从该全速时钟信号得到。在另一方面，分频时钟信号和全速时钟信号被分配到电子设备的IO电路。在另一方面，分频时钟信号也分配给电子设备的核心中的电路。

5. 发明申请

US20070058618A1 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US20070058618A1
公开(公告)日：2007-03-15
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H04L12/50
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

6. 发明授权

US06973221B1 Method and apparatus for reducing block related artifacts in video 失效
标题翻译：用于减少视频中块相关伪像的方法和装置
公开(公告)号：US06973221B1
公开(公告)日：2005-12-06
申请号：US09460965
申请日：1999-12-14
申请人： Ning Xue
发明人： Ning Xue
IPC分类号： G06T5/00 , H04N7/26
CPC分类号： H04N19/136 , H04N19/117 , H04N19/176
摘要： A method and apparatus for reducing block related artifacts in video are disclosed. A boundary is defined in a video frame between at least two or more sub-blocks where each of the sub-blocks contains a predetermined number of pixels. Pixels adjacent to the boundaries of the sub-blocks may be filtered to reduce blocking artifacts in the video. Pixel video values such as luma and chroma values may be utilized as input values to an anti-block filter. Average mean and average variance of the pixel video values in a sub-block are used to determined when anti-block filtering is applied. Pixels adjacent to the sub-block boundaries are filtered with an anti-block filtering algorithm in the event a predetermined condition is satisfied where the condition may be based upon the calculated average mean and average variance values. The filtering algorithm may include recalculating a pixel video value for pixels adjacent the sub-block boundaries. The invention may be utilized, for example, in converting MPEG-1 video to MPEG-2, and may be used in video devices such as VCD or DVD players, camcorders, etc. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种用于减少视频中的块相关伪影的方法和装置。在至少两个或多个子块之间的视频帧中定义边界，其中每个子块包含预定数量的像素。可以对与子块的边界相邻的像素进行滤波以减少视频中的块伪影。诸如亮度和色度值之类的像素视频值可以用作反块滤波器的输入值。使用子块中的像素视频值的平均平均和平均方差用于确定何时应用抗块滤波。在条件可以基于所计算的平均平均值和平均方差值的情况下满足预定条件的情况下，利用反块过滤算法来过滤与子块边界相邻的像素。滤波算法可以包括重新计算与子块边界相邻的像素的像素视频值。本发明可以用于例如将MPEG-1视频转换为MPEG-2，并且可以用于诸如VCD或DVD播放器，摄像机等的视频设备中。强调该摘要被提供以符合要求抽象的规则将允许搜索者或其他研究者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

7. 发明授权

US06334026B1 On-screen display format reduces memory bandwidth for time-constrained on-screen display systems 失效
标题翻译：屏幕显示格式可缩短时间有限的屏幕显示系统的内存带宽
公开(公告)号：US06334026B1
公开(公告)日：2001-12-25
申请号：US09105668
申请日：1998-06-26
申请人： Ning Xue , Takumi Nagasako , Manabu Gouzu
发明人： Ning Xue , Takumi Nagasako , Manabu Gouzu
IPC分类号： H04N5928
CPC分类号： H04N5/44504 , G11B20/10527 , G11B20/1251 , G11B27/3027 , G11B2020/10546 , G11B2020/1287 , G11B2220/2545 , G11B2220/2562 , H04N5/04 , H04N5/4401 , H04N5/602 , H04N5/765 , H04N5/775 , H04N5/85 , H04N9/8042 , H04N9/8063 , H04N21/42646 , H04N21/4307 , H04N21/4341 , H04N21/439
摘要： A multimedia decoder is provided that inserts synchronization words into elementary linear pulse-code modulation (LPCM) audio bitstreams. In one embodiment, the multimedia decoder includes a pre-parser, a memory, and an audio decoder module. The pre-parser receives a multimedia bitstream and separates it into an audio substream and a video substream, and inserts a synchronization words before each data packet in the audio substream while forming it into an elementary bitstream. The memory is coupled to the pre-parser to buffer the elementary audio bitstream, and the audio decoder module is coupled to the memory to retrieve the elementary audio bitstream and convert it into a digital audio signal. The inserted synchronization word may comprise between from four to ten bytes in length. In one particular implementation, the inserted synchronization word includes the ASCII representation of the letters LSILOGIC. The insertion and subsequent detection of a synchronization word in the elementary audio bitstream advantageously provides for robust synchronization in the presence of bitstream corruption while maintaining multimedia decoder modularity.
摘要翻译：提供了将同步字插入到基本线性脉码调制（LPCM）音频比特流中的多媒体解码器。在一个实施例中，多媒体解码器包括预解析器，存储器和音频解码器模块。预解析器接收多媒体比特流并将其分离成音频子流和视频子流，并且在音频子流中的每个数据分组之前插入同步字，同时将其形成为基本比特流。存储器耦合到预解析器以缓冲基本音频比特流，并且音频解码器模块耦合到存储器以检索基本音频比特流并将其转换成数字音频信号。插入的同步字可以包括长度在四到十个字节之间。在一个特定实现中，插入的同步字包括字母LSILOGIC的ASCII表示。基本音频比特流中的同步字的插入和后续检测有利地在存在比特流损坏的同时提供鲁棒同步，同时保持多媒体解码器的模块化。

8. 发明授权

US6112170A Method for decompressing linear PCM and AC3 encoded audio gain value 失效
标题翻译：解压缩线性PCM和AC3编码音频增益值的方法
公开(公告)号：US6112170A
公开(公告)日：2000-08-29
申请号：US105718
申请日：1998-06-26
申请人： Arvind Patwardhan , Ning Xue , Takumi Nagasako
发明人： Arvind Patwardhan , Ning Xue , Takumi Nagasako
IPC分类号： G10L19/08 , G10L19/00 , G10L21/04
CPC分类号： G10L19/083
摘要： An audio decoder which includes a coefficient memory and an arithmetic logic unit (ALU) can implement an efficient method for calculating a gain value specified by a range control field. In one embodiment, the audio decoder comprises coefficient memory, an ALU, frame control logic, and ALU control logic. The frame control logic extracts a range control field value from an audio packet header and provides it to the ALU control logic. The ALU control logic takes the binary representation of the range control field value and uses it to provide a sequence of addresses to the coefficient memory. In response to the sequence of addresses, the coefficient memory provides a sequence of pre-calculated factors to the ALU. The ALU control logic further directs the ALU to determine the product of the pre-calculated factors in the sequence. As a final step in finding the gain value, the ALU control logic may provide a shift instruction to the ALU. In one specific implementation, there is a maximum of three pre-calculated factors and one shift instruction required for one calculation of the gain value, and a required storage of only seven non-unity pre-calculated factors.
摘要翻译：包括系数存储器和算术逻辑单元（ALU）的音频解码器可以实现用于计算由范围控制字段指定的增益值的有效方法。在一个实施例中，音频解码器包括系数存储器，ALU，帧控制逻辑和ALU控制逻辑。帧控制逻辑从音频分组报头提取范围控制字段值，并将其提供给ALU控制逻辑。 ALU控制逻辑采用范围控制字段值的二进制表示，并使用它为系数存储器提供一系列地址。响应于地址序列，系数存储器向ALU提供一系列预先计算的因子。 ALU控制逻辑进一步指示ALU以确定序列中预先计算的因子的乘积。作为找到增益值的最后一步，ALU控制逻辑可以向ALU提供移位指令。在一个具体实现中，对于增益值的一个计算，存在最多三个预先计算的因子和一个移位指令，并且仅需要存储七个非统一预先计算的因子。

9. 发明授权

US6108622A Arithmetic logic unit controller for linear PCM scaling and decimation in an audio decoder 失效
标题翻译：用于音频解码器中线性PCM缩放和抽取的算术逻辑单元控制器
公开(公告)号：US6108622A
公开(公告)日：2000-08-22
申请号：US105719
申请日：1998-06-26
申请人： Ning Xue , Takumi Nagasako
发明人： Ning Xue , Takumi Nagasako
IPC分类号： G10L19/14 , G10L19/00 , G10L21/04
CPC分类号： G11B20/10527 , G10L19/008 , G11B2020/00021 , G11B2020/10546 , G11B2020/1062 , G11B2020/10685 , G11B2020/10694 , G11B2220/2537
摘要： An audio decoder converts a linear PCM audio data packet into two concurrently provided digital audio sample sequences: a high-quality sequence and a decimated sequence. In one embodiment, the audio decoder is part of an audio system that further includes two audio devices. The first audio device is configured to produce an audio signal from a 96 kHz sequence, and the second audio device expects a 48 kHz sequence. The audio decoder includes an input interface, an arithmetic logic unit (ALU), and two output buffers. The input interface is configured to receive a linear PCM audio data packet and to reconfigure bytes as necessary to reconstruct a sequence of unscaled audio samples. The ALU multiplies each of the unscaled audio samples by a gain factor and buffers the resulting scaled audio sample sequence in a first output buffer. After samples for two sampling instants have been processed, the ALU then retrieves a string of samples from the first output buffer, multiplies them by decimation filter coefficients, and adds the products to form decimation samples for one sampling instant. The decimation samples form a decimated audio sequence which is buffered in the second output buffer. The first output buffer provides the 96 kHz sequence to the first audio device, and the second output buffer provides the 48 kHz sequence to the second audio device. The sharing of the ALU between the scaling and decimation operations advantageously provides a versatile decoder at a minimal cost.
摘要翻译：音频解码器将线性PCM音频数据分组转换为两个同时提供的数字音频采样序列：高质量序列和抽取序列。在一个实施例中，音频解码器是还包括两个音频设备的音频系统的一部分。第一音频设备被配置为从96kHz序列产生音频信号，并且第二音频设备期望48kHz序列。音频解码器包括输入接口，算术逻辑单元（ALU）和两个输出缓冲器。输入接口被配置为接收线性PCM音频数据分组，并且根据需要重新配置字节以重构未缩放音频样本的序列。 ALU将每个未缩放的音频样本乘以增益因子，并将所得到的缩放音频采样序列缓冲在第一输出缓冲器中。在处理了两个采样时刻的样本之后，ALU然后从第一个输出缓冲器中取出一串样本，并将其乘以抽取滤波器系数，并将该乘积相加以形成一个抽样时刻的抽取样本。抽取样本形成缓冲在第二输出缓冲器中的抽取音频序列。第一个输出缓冲器为第一个音频设备提供96 kHz的序列，第二个输出缓冲区为第二个音频设备提供48 kHz的序列。在缩放和抽取操作之间共享ALU有利地以最小的成本提供通用解码器。

10. 发明授权

US08833737B2 Rackable fencing of components optimized for preassembly shipping 有权
标题翻译：组装运输优化组件的可拆卸围栏
公开(公告)号：US08833737B2
公开(公告)日：2014-09-16
申请号：US13351927
申请日：2012-01-17
申请人： Duane E. Langenwalter , Ning Xue
发明人： Duane E. Langenwalter , Ning Xue
IPC分类号： E04H17/14
CPC分类号： E04H17/1426
摘要： A rackable fence with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.
摘要翻译：带有轨道，支架托架和多个支架的可机架围栏。导轨限定了刚性的倒U形横截面。支架载体包括位于轨道内部并延伸穿过轨道内部的顶部跨距。支杆可枢转地附接到支架托架并且能够朝向轨道枢转。

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