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31. 发明申请

US20110032745A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110032745A1
公开(公告)日：2011-02-10
申请号：US12846198
申请日：2010-07-29
申请人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明实施例的一个方面的非易失性半导体存储器件还包括用于选择给定的一个存储单元的控制器，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

32. 发明申请

US20100213550A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100213550A1
公开(公告)日：2010-08-26
申请号：US12556005
申请日：2009-09-09
申请人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
发明人： Hiroshi Kanno , Kenichi Murooka , Jun Hirota , Hideyuki Tabata
IPC分类号： H01L27/10
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/1027
摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Sii-xGex (0
摘要翻译：存储单元位于第一布线和第二布线之间的相应交点处。每个存储单元具有串联连接的整流元件和可变电阻元件。整流元件包括p型第一半导体区域和n型第二半导体区域。第一半导体区域至少部分地由硅 - 锗混合物（Sii-xGex（0

33. 发明授权

US07379324B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07379324B2
公开(公告)日：2008-05-27
申请号：US11147323
申请日：2005-06-08
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C23/00 , G11C2213/71 , G11C2213/77
摘要： The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.
摘要翻译：本发明提供了一种存储装置，其包括第一电极，跨越间隙与第一电极相对布置的多个第二电极和选择性地放置在第一电极和第二电极之间的间隙之一中并且可移动的在第一电极和第二电极之间以及相邻的第二电极之间。使用颗粒的存在来确定存储状态。

34. 发明申请

US20070291539A1 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070291539A1
公开(公告)日：2007-12-20
申请号：US11699334
申请日：2007-01-30
申请人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
发明人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
IPC分类号： G11C11/34 , H01L21/822
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译：非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域位置高她比第三个导电区域。

35. 发明申请

US20070212488A1 Pattern transfer method and pattern transfer apparatus 审中-公开
标题翻译：图案转印方式和图案转印装置
公开(公告)号：US20070212488A1
公开(公告)日：2007-09-13
申请号：US11522397
申请日：2006-09-18
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： B05D5/00 , C03C25/68 , B05C1/00
CPC分类号： G03F9/7003 , G03F9/703 , G03F9/7038
摘要： A pattern transfer method includes performing positioning between a transfer position of a pattern forming surface of a transfer original plate on which a pattern to be transferred is formed and a transferred position of a transferred surface of a transferred substrate to which the pattern is to be transferred; contacting the pattern forming surface with the transferred surface; and partly correcting the positional deviation between the transfer position of the pattern forming surface and the transferred position of the transferred surface in the in-plane direction, after the positioning is performed.
摘要翻译：图案转印方法包括在其上形成有转印图案的转印原版的图案形成表面的转印位置与转印的图案的转印基板的转印表面的转印位置之间进行定位 ; 使图案形成表面与转印表面接触; 并且在进行定位之后，部分地校正图案形成表面的转印位置和转印表面在面内方向上的转印位置之间的位置偏差。

36. 发明申请

US20070047323A1 Storage apparatus and manufacturing method thereof 失效
标题翻译：储存装置及其制造方法
公开(公告)号：US20070047323A1
公开(公告)日：2007-03-01
申请号：US11501897
申请日：2006-08-10
申请人： Kenichi Murooka , Toshiro Hiraoka
发明人： Kenichi Murooka , Toshiro Hiraoka
IPC分类号： G11C11/34
CPC分类号： G11C11/22 , G11C11/221 , G11C23/00
摘要： A method of manufacturing a storage apparatus includes preparing a first substrate on which a plurality of row lines are arranged in parallel, preparing a second substrate on which a plurality of column lines are arranged in parallel, dispensing as a droplet a solution, in which particles are dispersed in a solvent, from a solution supply port to which an electric field is applied, toward a surface of the first substrate or a surface of the second substrate, and arranging the surfaces of the first and second substrates to face each other with a gap such that the column lines cross the row lines, thereby making the particles at crossing portions to be movable between the row lines and the column lines facing each other and between the crossing portions adjacent to each other.
摘要翻译：一种存储装置的制造方法，其特征在于，准备并列配置有多条行线的第一基板，准备并列配置有多条列线的第二基板，以液滴的形式配置粒子从施加有电场的溶液供给口朝向第一基板的表面或第二基板的表面分散在溶剂中，并且使第一基板和第二基板的表面彼此面对间隙，使得列线与行线交叉，从而使得交叉部分处的粒子能够在彼此相对的行线和列线之间以及彼此相邻的交叉部分之间移动。

37. 发明授权

US08760908B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08760908B2
公开(公告)日：2014-06-24
申请号：US13235431
申请日：2011-09-18
申请人： Tetsuji Kunitake , Kenichi Murooka
发明人： Tetsuji Kunitake , Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C8/14 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C2013/0076 , G11C2213/71
摘要： A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first and second decoders and which applies a predetermined voltage between the first and second lines selected by the first and second decoders. The second decoder sequentially selects the second lines in a direction from the other ends to the one ends of the first lines.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列，其具有多个第一线，与多条第一线相交的多条第二线，以及存储电可重写电阻值作为非易失性数据的多个存储单元方式; 第一解码器，其连接到所述多个第一线的一端并选择所述第一线; 第二解码器，连接到所述多个第二线并选择所述第二线; 以及电压施加电路，其连接到第一和第二解码器中的一个，并且在由第一和第二解码器选择的第一和第二线之间施加预定电压。第二解码器从第一行的另一端到一端的方向依次选择第二行。

38. 发明授权

US08570786B2 Memory device and fabricating method thereof 有权
公开(公告)号：US08570786B2
公开(公告)日：2013-10-29
申请号：US13177857
申请日：2011-07-07
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.

39. 发明授权

US08295077B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08295077B2
公开(公告)日：2012-10-23
申请号：US13001147
申请日：2009-06-11
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0054 , G11C2213/71 , H01L27/115 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A semiconductor memory device comprises a plurality of first row lines arranged in parallel; a plurality of column lines intersecting the first row lines; a plurality of storage elements arranged at intersections of the first row lines and the column lines; a plurality of second row lines arranged in parallel with the first row lines, from positions opposite to the first row lines via the column lines to a certain portion of the column line, and capacitively coupled with the column lines; and a sense amplifier including a field effect transistor having a lower layer control electrode composed of the certain portion of the column line, and an upper layer control electrode composed of the second row line capacitively coupled in the upper layer with the certain portion of the column line.
摘要翻译：半导体存储器件包括并行布置的多个第一行线; 与第一行线相交的多个列线; 多个存储元件，布置在第一行线和列线的交点处; 多条第二行线，与第一行线平行排列，从与第一列行相对的位置经由列线排列到列线的某一部分，并与列线电容耦合; 以及包括具有由列线的特定部分组成的下层控制电极的场效应晶体管的读出放大器，以及由上层的电容耦合到列的一定部分的第二行线构成的上层控制电极线。

40. 发明授权

US08086107B2 Optical-electrical hybrid integrated circuit 有权
标题翻译：光电混合集成电路
公开(公告)号：US08086107B2
公开(公告)日：2011-12-27
申请号：US12033330
申请日：2008-02-19
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： H04B10/00
CPC分类号： H04B10/801 , G02B6/43
摘要： An operating unit performs a prescribed operation and includes a standby-state-signal generating unit that generates a standby state signal for switching between a standby state and an operation state of the operating unit in a first part of the operating unit. An optical-signal transmitting unit converts an electric signal, which is a result of the operation in a second part of the operating unit, into an optical signal, transmits the optical signal to a third part of the operating unit, and then converts the optical signal into the electric signal. A power-supply control unit controls a supply of the electric power to the operating unit and a supply of the electric power to the optical-signal transmitting unit by a power supply unit in response to the standby state signal.
摘要翻译：操作单元执行规定的操作，并且包括在操作单元的第一部分中产生用于在待机状态和操作单元的操作状态之间切换的待机状态信号的待机状态信号生成单元。光信号发送单元将作为操作单元的第二部分的操作结果的电信号转换为光信号，将光信号发送到操作单元的第三部分，然后将光信号信号进入电信号。电源控制单元控制对操作单元的电力供应，并且响应于待机状态信号，通过电源单元向光信号发送单元供应电力。

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