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31. 发明授权

US07782935B1 Half-rate DFE with duplicate path for high data-rate operation 有权
标题翻译：具有高数据速率操作的重复路径的半速率DFE
公开(公告)号：US07782935B1
公开(公告)日：2010-08-24
申请号：US11514490
申请日：2006-08-31
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H04L25/03878 , H04L2025/0349
摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.
摘要翻译：提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。可以使用以输入信号数据速率的一半工作的两个延迟链电路。更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

32. 发明授权

US08416001B2 Techniques for reducing duty cycle distortion in periodic signals 有权
标题翻译：降低周期信号中占空比失真的技术
公开(公告)号：US08416001B2
公开(公告)日：2013-04-09
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

33. 发明授权

US07429897B1 Wide operating-frequency range voltage controlled oscillators 有权
标题翻译：宽工作频率范围的压控振荡器
公开(公告)号：US07429897B1
公开(公告)日：2008-09-30
申请号：US11514489
申请日：2006-08-31
申请人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
发明人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
IPC分类号： H03B5/08
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00202 , H03L7/0995 , H03L2207/06
摘要： Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.
摘要翻译：介绍了具有低相位噪声和宽范围工作频率的压控振荡器（VCO）电路。 VCO电路包括具有两个或多个VCO子电路的电路，每个子电路被优化以产生具有低相位噪声和频率在不同范围内的输出时钟信号。具有齿轮输入的子电路可以用于产生在较低频率范围内的输出时钟信号，而针对高速操作优化的子电路可用于产生较高频率范围内的输出信号。控制电路可用于产生耦合到所有子电路的控制信号。控制信号可以设定子电路的工作频率。

34. 发明授权

US08120429B1 Voltage-controlled oscillator methods and apparatus 有权
标题翻译：压控振荡器的方法和装置
公开(公告)号：US08120429B1
公开(公告)日：2012-02-21
申请号：US12787722
申请日：2010-05-26
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L7/00 , H03K3/03
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译：提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

35. 发明授权

US07514968B1 H-tree driver circuitry 有权
标题翻译： H树驱动电路
公开(公告)号：US07514968B1
公开(公告)日：2009-04-07
申请号：US11786295
申请日：2007-04-10
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.
摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

36. 发明授权

US07436228B1 Variable-bandwidth loop filter methods and apparatus 失效
标题翻译：可变带宽环路滤波器的方法和装置
公开(公告)号：US07436228B1
公开(公告)日：2008-10-14
申请号：US11317126
申请日：2005-12-22
申请人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
发明人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong
IPC分类号： H03K5/00 , H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.
摘要翻译：提供了用于改变环路电路（例如，锁相环电路）中的环路滤波器的带宽的方法和装置。环路滤波器可以包括耦合到电容器的第一和第二电阻器电路。响应于操作模式的选择，电阻器电路中的一个可以耦合到环路电路的输出。电阻器电路可以各自包括可以选择性地串联耦合到电容器或绕过的多个电阻器。此外，环路电路的输出可以耦合到第二电容器。电容器中的任一个或两个可以是可编程的。

37. 发明授权

US08175143B1 Adaptive equalization using data level detection 有权
标题翻译：使用数据级检测的自适应均衡
公开(公告)号：US08175143B1
公开(公告)日：2012-05-08
申请号：US12037284
申请日：2008-02-26
申请人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
发明人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03356 , H04L2025/03745 , H04L2025/03783
摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.
摘要翻译：用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机以提取用于数字化的参考电平并控制均衡曲线。参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。状态机优选是可编程的。这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

38. 发明申请

US20120256670A1 Techniques for Reducing Duty Cycle Distortion in Periodic Signals 有权
标题翻译：降低周期信号占空比变形的技术
公开(公告)号：US20120256670A1
公开(公告)日：2012-10-11
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

39. 发明授权

US07956696B2 Techniques for generating fractional clock signals 有权
$Techniques for generating fractional clock signals$
标题翻译：产生分数时钟信号的技术
公开(公告)号：US07956696B2
公开(公告)日：2011-06-07
申请号：US12234114
申请日：2008-09-19
申请人： Tim Tri Hoang , Wilson Wong , Sergey Shumarayev
发明人： Tim Tri Hoang , Wilson Wong , Sergey Shumarayev
IPC分类号： H03L7/085 , H03B19/00
CPC分类号： H03L7/099 , H03L7/18
摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.
摘要翻译：电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。时钟信号产生电路响应于控制信号产生周期性输出信号。第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

40. 发明授权

US07728674B1 Voltage-controlled oscillator methods and apparatus 失效
标题翻译：压控振荡器的方法和装置
公开(公告)号：US07728674B1
公开(公告)日：2010-06-01
申请号：US11437558
申请日：2006-05-19
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译：提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

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