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31. 发明授权

US07541858B2 Integration circuit, decrement circuit, and semiconductor devices 有权
标题翻译：集成电路，减量电路和半导体器件
公开(公告)号：US07541858B2
公开(公告)日：2009-06-02
申请号：US11187862
申请日：2005-07-25
申请人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
发明人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
IPC分类号： G06G7/18 , G06F7/64
CPC分类号： F02P3/0552
摘要： An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitor 1 capable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuit 12 whose rise output is applied to the gate of a self-shutdown MOSFET 33 via an integration circuit 33 comprised of a diode 8 and a capacitor 9. The gate voltage of IGBT 5a, which is a main-current switching device, can be decremented.
摘要翻译：包括具有毫秒级时间常数且具有最小电路尺寸和面积的电路的点火器，其能够在检测到异常时自动关闭而不导致错误点火。能够在检测到异常时能够自我关机的点火器1包括：异常检测电路12，其上升输出经由由二极管8和电容器9组成的积分电路33施加到自停闭MOSFET 33的栅极。作为主电流开关器件的IGBT 5a的栅极电压可以减小。

32. 发明申请

US20060022609A1 Integration circuit, decrement circuit, and semiconductor devices 有权
标题翻译：集成电路，减量电路和半导体器件
公开(公告)号：US20060022609A1
公开(公告)日：2006-02-02
申请号：US11187862
申请日：2005-07-25
申请人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
发明人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
IPC分类号： F02P15/00 , F02P3/04
CPC分类号： F02P3/0552
摘要： An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitor 1 capable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuit 12 whose rise output is applied to the gate of a self-shutdown MOSFET 33 via an integration circuit 33 comprised of a diode 8 and a capacitor 9. The gate voltage of IGBT 5a, which is a main-current switching device, can be decremented.
摘要翻译：包括具有毫秒级时间常数且具有最小电路尺寸和面积的电路的点火器，其能够在检测到异常时自动关闭而不导致错误点火。能够在检测到异常时能够自我关机的点火器1包括：异常检测电路12，其上升输出经由由二极管8和电容器9组成的积分电路33施加到自停闭MOSFET 33的栅极。作为主电流开关器件的IGBT5a的栅极电压可以减小。

33. 发明授权

US06539928B2 Vehicle-mounted ignitor 失效
公开(公告)号：US06539928B2
公开(公告)日：2003-04-01
申请号：US09790544
申请日：2001-02-23
申请人： Yasuhiko Kohno , Junpei Uruno , Mutsuhiro Mori
发明人： Yasuhiko Kohno , Junpei Uruno , Mutsuhiro Mori
IPC分类号： F02P300
CPC分类号： F02P3/04 , F02P3/0552
摘要： A circuit for supplying an oscillation suppress current is provided between a collector terminal and gate electrode of a main IGBT. The current supply circuit comprises a resistor and a diode which are connected in series. A bypass MOSFET is connected between the series connection and the emitter terminal. No semiconductor element having different temperature characteristics is provided in the current supply circuit.

34. 发明授权

US06304472B1 Electric power converting system with integrator providing output indicative of current 有权
标题翻译：具有积分器的电力转换系统提供指示电流的输出
公开(公告)号：US06304472B1
公开(公告)日：2001-10-16
申请号：US09570034
申请日：2000-05-12
申请人： Masahiro Nagasu , Shin Kimura , Mutsuhiro Mori , Kiyoshi Nakata , Mutsuhiro Terunuma
发明人： Masahiro Nagasu , Shin Kimura , Mutsuhiro Mori , Kiyoshi Nakata , Mutsuhiro Terunuma
IPC分类号： H02M324
CPC分类号： H02M7/53871 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H02M7/003 , H02M2001/0009 , H01L2924/00014
摘要： In order to detect a current with high accuracy in an electric power converting system, an inductor is connected to a main terminal of a switching element in series, and a voltage generated in both ends of the inductor during switching period is integrated using an integrating circuit to detect the current.
摘要翻译：为了在电力转换系统中高精度地检测电流，将电感器串联连接到开关元件的主端子，并且在开关周期期间在电感器的两端产生的电压使用积分电路检测电流。

35. 发明授权

US06275399B1 Method and apparatus for driving a semiconductor element with variable resistance circuitry 失效
标题翻译：用可变电阻电路驱动半导体元件的方法和装置
公开(公告)号：US06275399B1
公开(公告)日：2001-08-14
申请号：US09654892
申请日：2000-09-05
申请人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
发明人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
IPC分类号： H02M768
CPC分类号： H03K17/0822 , H03K17/165
摘要： In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.
摘要翻译：在用于导通或中断主电流的功率半导体元件的驱动装置中，根据控制电压改变第一电阻的第一电阻变量，以及根据第一和第二电压之间的电压来改变第二电阻的第二电阻变量端子，并且控制电源的电压或第一和第二端子之间的电压中的任一个被第一电阻和第二电阻分压，并且分压被施加到控制栅极端子执行或中断主电流的时间。

36. 发明授权

US06204717B1 Semiconductor circuit and semiconductor device for use in equipment such as a power converting apparatus 失效
标题翻译：用于诸如电力转换装置的设备的半导体电路和半导体器件
公开(公告)号：US06204717B1
公开(公告)日：2001-03-20
申请号：US08651875
申请日：1996-05-21
申请人： Masahiro Nagasu , Hideo Kobayashi , Hideki Miyazaki , Shin Kimura , Junichi Sakano , Mutsuhiro Mori
发明人： Masahiro Nagasu , Hideo Kobayashi , Hideki Miyazaki , Shin Kimura , Junichi Sakano , Mutsuhiro Mori
IPC分类号： H03K508
CPC分类号： H01L29/866 , H01L29/0692 , H01L29/0834 , H01L29/7393 , H01L29/7395 , H03K17/08148 , H03K17/0828
摘要： A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby prevent the occurrence of the electromagnetic noise and the excessively large voltage.
摘要翻译：半导体电路或半导体器件具有电流 - 电压特性，在半导体电路或半导体器件的阻挡状态下，电流缓慢地流过等于或大于第一电压值但等于或等于或小于第二电压，而电流突然流过大于第二电压值的电压值。由于电流 - 电压特性，电路中提供的电感中积累的能量被半导体电路或半导体的差分电阻消耗，从而防止电磁噪声的发生和过大的电压。

37. 发明授权

US5767555A Compound semiconductor device controlled by MIS gate, driving method therefor and electric power conversion device using the compound semiconductor device and the driving method 失效
标题翻译：由MIS门控制的复合半导体器件，其驱动方法和使用该化合物半导体器件的驱动方法和电力转换器件
公开(公告)号：US5767555A
公开(公告)日：1998-06-16
申请号：US612457
申请日：1996-03-07
申请人： Junichi Sakano , Hideo Kobayashi , Masahiro Nagasu , Mutsuhiro Mori
发明人： Junichi Sakano , Hideo Kobayashi , Masahiro Nagasu , Mutsuhiro Mori
IPC分类号： H01L29/10 , H01L29/745 , H01L29/749 , H01L29/76
CPC分类号： H01L29/7455 , H01L29/102 , H01L29/749
摘要： A compound semiconductor device including a MISFET and a thyristor connected in series wherein either the withstanding voltage between the MISFET p base layer and the thyristor p base layer is set lower than the withstanding voltage of the MISFET, the MISFET is turned off under a condition that the MISFET p base layer and the thyristor p base layer are connected via a p channel or the lateral resistance of the thyristor p base layer is reduced, thereby the safe operating region of the compound semiconductor device is extended.
摘要翻译：一种复合半导体器件，包括MISFET和串联连接的晶闸管，其中MISFET p基极层和晶闸管p基极层之间的耐受电压设定为低于MISFET的耐受电压，MISFET在以下条件下关断： MISFET p基极层和晶闸管p基极层通过ap沟道连接，或者晶闸管p基极层的横向电阻降低，从而延长了化合物半导体器件的安全工作区域。

38. 发明授权

US5701018A Semiconductor device having parallel connection of an insulated gate bipolar transistor and a diode 失效
标题翻译：具有绝缘栅双极晶体管和二极管的并联连接的半导体器件
公开(公告)号：US5701018A
公开(公告)日：1997-12-23
申请号：US391568
申请日：1995-02-21
申请人： Koumei Hanaoka , Naoki Sakurai , Mutsuhiro Mori
发明人： Koumei Hanaoka , Naoki Sakurai , Mutsuhiro Mori
IPC分类号： H01L25/07 , H01L29/739 , H01L29/861 , H02J7/00 , H01L29/74 , H01L29/76 , H01L31/111 , H02H7/122
CPC分类号： H01L29/7395 , H01L25/072 , H01L2224/48091 , H01L29/861 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H02J7/0029
摘要： The present invention provides a semiconductor device comprising, at least a pair of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from conduction state to blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of blocking state.
摘要翻译：本发明提供了一种半导体器件，其包括至少一对绝缘栅双极晶体管和二极管，它们都彼此反向并联连接，其中基极层的最低杂质浓度的电阻率二极管低于绝缘栅双极晶体管中最低杂质浓度的基极层的二极管，并且其中在从导通状态切换到阻断状态时所述绝缘栅双极晶体管的击穿电压低于击穿电压的所述绝缘栅双极晶体管和所述二极管。

39. 发明授权

US5670811A Vertical insulated gate semiconductor device having high current density and high reliability 失效
标题翻译：具有高电流密度和高可靠性的垂直绝缘栅半导体器件
公开(公告)号：US5670811A
公开(公告)日：1997-09-23
申请号：US430289
申请日：1995-04-28
申请人： Mutsuhiro Mori , Tomoyuki Tanaka , Yasumichi Yasuda , Yasunori Nakano
发明人： Mutsuhiro Mori , Tomoyuki Tanaka , Yasumichi Yasuda , Yasunori Nakano
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66333 , H01L21/2257 , H01L29/66712 , H01L29/7395 , H01L29/7802
摘要： The present invention is directed to a semiconductor device which can achieve high current density and which has a high reliability. In the insulated gate semiconductor device according to the present invention, a plurality of insulating gates are provided, with each two adjacent insulating gates being spaced from each other, the insulating gates being provided on a second semiconductor region of a first conductivity type. A first semiconductor region, of the same or different conductivity type from that of the second semiconductor region, extends from a surface of the second semiconductor region opposed to the surface thereof having the insulating gates thereon. A plurality of third semiconductor regions are provided in the second semiconductor region, between the insulating gates and aligned therewith, and two fourth semiconductor regions are provided extending into each of the third semiconductor regions, aligned with the sides of adjacent insulating gates. Electrodes are respectively provided in contact with the first semiconductor region and in contact with the third and fourth semiconductor regions, the electrode in contact with the third and fourth semiconductor regions contacting such regions in the space between adjacent insulating gates. By utilizing such aligned third and fourth semiconductor regions, an insulated gate semiconductor device which operates at high current densities can be fabricated at high accuracy, and such device will be less influenced by parasitic bipolar transistor effects.
摘要翻译：本发明涉及能够实现高电流密度并且具有高可靠性的半导体器件。在根据本发明的绝缘栅半导体器件中，设置有多个绝缘栅极，每个两个相邻的绝缘栅极彼此间隔开，绝缘栅极设置在第一导电类型的第二半导体区域上。与第二半导体区域相同或不同的导电类型的第一半导体区域从与其上具有绝缘栅极的表面相对的第二半导体区域的表面延伸。多个第三半导体区域设置在第二半导体区域中，在绝缘栅极之间并与其对准，并且提供两个第四半导体区域，其延伸到每个第三半导体区域中，与相邻绝缘栅极的侧面对准。电极分别设置成与第一半导体区域接触并且与第三和第四半导体区域接触，与第三和第四半导体区域接触的电极与相邻绝缘栅极之间的空间中的这些区域接触。通过利用这种对准的第三和第四半导体区域，可以以高精度制造以高电流密度工作的绝缘栅极半导体器件，并且这种器件将受寄生双极晶体管效应的影响较小。

40. 发明授权

US5357120A Compound semiconductor device and electric power converting apparatus using such device 失效
标题翻译：使用这种装置的复合半导体器件和电力转换装置
公开(公告)号：US5357120A
公开(公告)日：1994-10-18
申请号：US912989
申请日：1992-07-14
申请人： Mutsuhiro Mori
发明人： Mutsuhiro Mori
IPC分类号： H01L27/06 , H01L29/745 , H01L29/749 , H02H7/122 , H01L29/10 , H01L29/74
CPC分类号： H01L29/749 , H01L27/0623 , H01L29/7455
摘要： A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.
摘要翻译：提供了一种化合物半导体器件，其包括由四个连续的p-n-p-n层构成的晶闸管区域和形成在晶闸管区域的中间n层中以远离中间p层的MOSFET区域。 MOSFET由p阱层，源极层和漏极层构成。器件的一个主电极与晶闸管区域的外部p层欧姆接触。而另一个主电极与MOSFET区域的源极层和阱层欧姆接触。提供了用于电连接晶闸管区域的外部n层和MOSFET区域的漏极层的布置。此外，在MOSFET区域的源极层和漏极层之间的阱层上形成第一绝缘栅极，在晶闸管区域的中间p层上形成第二绝缘栅极; 第一绝缘栅极和第二绝缘栅极电连接。

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