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    • 31. 发明授权
    • System and memory for sequential multi-plane page memory operations
    • 用于顺序多平面页面存储器操作的系统和存储器
    • US08289802B2
    • 2012-10-16
    • US13051221
    • 2011-03-18
    • June Lee
    • June Lee
    • G11C8/00
    • G11C16/10G11C5/02G11C2216/14
    • A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
    • 一种用于在多平面闪存中执行存储器操作的系统和方法。 命令和地址被顺序地提供给存储器以用于存储器平面中的存储器操作。 顺序地启动存储器操作,并且在另一存储器平面的存储器操作期间启动至少一个存储器平面的存储器操作。 在一个实施例中,多个编程电路中的每一个与相应的存储器平面相关联,并且可操作以响应于编程信号将数据编程到相应的存储器平面,并且当其被启用时。 耦合到多个编程电路的控制逻辑响应于存储器接收程序命令而产生编程信号,并进一步产生编程使能信号,以单独使编程电路中的每一个能够对编程信号做出响应,并将数据错开编程到每个存储器 飞机
    • 32. 发明申请
    • MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM
    • 用于图形处理系统的读取和写入带宽的改进的存储器系统和方法
    • US20120242670A1
    • 2012-09-27
    • US13487802
    • 2012-06-04
    • William Radke
    • William Radke
    • G06T1/20G06F13/00
    • G09G5/39G09G2360/123
    • A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.
    • 用于处理图形数据的系统。 图形处理系统包括嵌入式存储器阵列,其具有存储图形数据的至少三个独立的单端口存储器组。 耦合到存储体的存储器控​​制器将从第二存储器存储器读取数据的后处理数据写入第一存储体。 同步图形处理流水线处理从第二存储体读出的数据,并将后处理的图形数据提供给存储器控制器以写回存储体。 处理流水线同时处理至少等于包含在存储器页面中的数量的图形数据。 当从第二存储器存储器读取数据完成时,第三存储器组同时对第一存储体写入数据并从第二存储体读取数据以准备访问。
    • 34. 发明授权
    • Applying epitaxial silicon in disposable spacer flow
    • 在一次性间隔流中应用外延硅
    • US08232167B2
    • 2012-07-31
    • US13019540
    • 2011-02-02
    • Chin-Chen ChoEr-Xuan Ping
    • Chin-Chen ChoEr-Xuan Ping
    • H01L21/8234
    • H01L27/10894H01L21/28525H01L21/823418H01L21/823468H01L21/823481H01L27/105H01L27/10873H01L27/11526H01L27/11546H01L29/66636
    • A method of fabricating transistors on a semiconductor substrate includes forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively. The transistor gates have generally vertical sidewalls. Source and drain regions are simultaneously formed for the first and second transistors. Temporary spacers are formed on the vertical sidewalls of the first and second transistor gates. The temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered. The temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed. The semiconductor substrate is exposed to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors.
    • 在半导体衬底上制造晶体管的方法包括分别形成位于半导体衬底的第一和第二区域中的第一和第二晶体管的晶体管栅极。 晶体管栅极具有大致垂直的侧壁。 源极和漏极区同时形成用于第一和第二晶体管。 临时间隔件形成在第一和第二晶体管栅极的垂直侧壁上。 第一晶体管的临时间隔物邻接半导体结构,使得第一晶体管的源极和漏极区域被垂直覆盖。 第二晶体管的临时间隔物覆盖第二晶体管的源区和漏区的一部分,使得源区和漏区的一部分保持暴露。 将半导体衬底暴露于注入掺杂剂以改变第二晶体管的源极和漏极区域的暴露部分的掺杂剂水平。
    • 35. 发明授权
    • System and method to improve the efficiency of synchronous mirror delays and delay locked loops
    • 提高同步镜像延迟和延迟锁定环路效率的系统和方法
    • US08212595B2
    • 2012-07-03
    • US12574847
    • 2009-10-07
    • Feng Lin
    • Feng Lin
    • H03L7/00
    • G11C7/222G06F1/10G11C7/22H03L7/0814
    • A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.
    • 公开了一种用于同步镜延迟或延迟锁定环路的相位检测系统,以便减少所需的延迟级数,从而提高效率。 本发明包括采用每个具有定时特性的时钟输入信号和时钟延迟或反馈信号,并且基于信号的定时特性来区分四个条件。 相位检测器和相关电路然后基于信号的定时特性来确定信号处于多个相位条件中的哪一个。选择器通过定时选择要被引入同步镜延迟或延迟锁定环路的信号 相位条件的特征。 该系统能够利用时钟输入信号的下降时钟边沿,并且在特定相位条件下锁定时间减少。 本发明通过在保持工作范围的同时减少SMD或DLL中的有效延迟级来提高电路的效率。
    • 36. 发明授权
    • Method and system for filtering unauthorized electronic mail messages
    • 用于过滤未经授权的电子邮件消息的方法和系统
    • US08209387B2
    • 2012-06-26
    • US12642577
    • 2009-12-18
    • Hoyt A. Fleming, III
    • Hoyt A. Fleming, III
    • G06F15/16G06F17/30
    • H04L51/22G06Q10/107H04L51/12H04L63/126Y10S707/99943Y10S707/99945
    • A computer system and method for filtering unauthorized electronic mail messages that are sent by senders to a user. The system includes a list of the identifications of the senders who are authorized to send an electronic mail message to the user. When an electronic mail message is received, the system determines whether the sender of the electronic mail message is authorized by determining whether the identification of sender in the electronic mail message is in the list of the identifications of the senders who are authorized. When the sender of the electronic mail message is determined to be authorized, the system stores the electronic mail message in an Inbox folder. When the sender of the electronic mail message is determined to be not authorized, the system stores the electronic mail message in a Junk Mail folder. In this way, the electronic mail messages are automatically stored in the appropriate folder based on whether the sender is authorized so that the user can view the Inbox folder containing the electronic mail messages sent by authorized senders separately from the Junk Mail folder containing the electronic mail messages sent by unauthorized senders.
    • 一种用于过滤由发送者发送给用户的未经授权的电子邮件消息的计算机系统和方法。 该系统包括被授权向用户发送电子邮件消息的发送者的标识的列表。 当接收到电子邮件消息时,系统通过确定电子邮件消息中的发件人的身份是否在被授权的发件人的标识的列表中来确定电子邮件消息的发送者是否被授权。 当确定电子邮件消息的发送者被授权时,系统将电子邮件消息存储在收件箱文件夹中。 当电子邮件消息的发送者被确定为不被授权时,系统将电子邮件消息存储在垃圾邮件文件夹中。 以这种方式,电子邮件消息将根据发件人是否被授权自动存储在适当的文件夹中,以便用户可以查看包含由授权发件人发送的电子邮件消息的收件箱文件夹,该垃圾邮件文件夹与包含电子邮件的垃圾邮件文件夹分开 未经授权的发件人发送的邮件。
    • 38. 发明申请
    • FAST AND COMPACT CIRCUIT FOR BUS INVERSION
    • 用于总线反向的快速和紧凑电路
    • US20120131251A1
    • 2012-05-24
    • US13361291
    • 2012-01-30
    • Mayur Joshi
    • Mayur Joshi
    • G06F13/14
    • G06F13/4217G06F7/501Y02D10/14Y02D10/151
    • A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.
    • 一种基于处理器的系统,具有至少一个处理器,至少一个存储器控制器以及可选的其它设备,其具有在负责总线反转决定的电路中具有快速且紧凑的多数选民的总线系统。 多数选民在具有两个分支的模拟电路中实现。 一个分支总结了在不反转的情况下发送比特的优点,另外一个总结了利用反演发送比特的优点。 多数选民通过同时比较每个分支中的当前驱动器来计算略微多于一个门延迟的总线反转决定。
    • 39. 再颁专利
    • Method of addressing messages and communications systems
    • USRE43382E1
    • 2012-05-15
    • US12701563
    • 2010-02-07
    • Clifton W. Wood, Jr.
    • Clifton W. Wood, Jr.
    • H04W4/00
    • H04W4/00
    • A method of and apparatus for establishing wireless communications between an interrogator and individual ones of multiple wireless identification devices, the method comprising utilizing a tree search method to establish communications without collision between the interrogator and individual ones of the multiple wireless identification devices, a search tree being defined for the tree search method, the tree having multiple levels respectively representing subgroups of the multiple wireless identification devices, the method further comprising starting the tree search at a selectable level of the search tree. A communications system comprising an interrogator, and a plurality of wireless identification devices configured to communicate with the interrogator in a wireless fashion, the respective wireless identification devices having a unique identification number, the interrogator being configured to employ a tree search technique to determine the unique identification numbers of the different wireless identification devices so as to be able to establish communications between the interrogator and individual ones of the multiple wireless identification devices without collision by multiple wireless identification devices attempting to respond to the interrogator at the same time, wherein the interrogator is configured to start the tree search at a selectable level of the search tree. In one embodiment, the interrogator transmits a first request indicating a subgroup of random numbers out of a total number of possible random numbers. The wireless identification devices each determine if the random number generated by each wireless identification device falls within the subgroup, and if so, the wireless identification device responds to the interrogator. If a collision between wireless identification device responses is detected by the interrogator, the interrogator transmits a second request indicating a subgroup of random numbers.