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31. 发明申请

US20100325600A1 ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN 有权
标题翻译：在分层电路设计中通过电路块布线网络
公开(公告)号：US20100325600A1
公开(公告)日：2010-12-23
申请号：US12490023
申请日：2009-06-23
申请人： Yi Wu , Dajen Huang , Kalon S. Holdbrook
发明人： Yi Wu , Dajen Huang , Kalon S. Holdbrook
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.
摘要翻译：本发明的一些实施例提供一种在分层电路设计中将网络路由到电路块上的系统。在运行期间，系统可以接收一组电路块。电路块的至少一些端子可能期望使用期望在一个或多个电路块上布线的网电连接在一起。系统可以将与块（例如，位于块之上的金属层中的区域）相关联的区域划分成一组瓦片。接下来，系统可以将成本分配给该组瓦片中的至少一些瓦片。然后，系统可以在路由期间使用成本。请注意，在路由期间使用瓦片的成本使得缓冲区更有可能在需要满足压缩和时序要求的地方使用。

32. 发明申请

US20100306236A1 Data Policy Management System and Method for Managing Data 审中-公开
标题翻译：数据管理系统和数据管理方法
公开(公告)号：US20100306236A1
公开(公告)日：2010-12-02
申请号：US12474663
申请日：2009-05-29
申请人： Joseph M. Cychosz , Harriet Gladys Coverston
发明人： Joseph M. Cychosz , Harriet Gladys Coverston
IPC分类号： G06F17/30
CPC分类号： G06F16/122
摘要： A method for managing data includes identifying nodes of an archiving file system executing on one or more computers that have been updated, acquiring time ordered node state change events within the archiving file system, storing the node state change events, and reading the stored node state change events. The method further includes acquiring current information contained within the nodes that has been updated, updating data contained within a database system executing on the one or more computers to reflect the acquired information, querying the database system, and enforcing data policies upon the archiving file system based on the results of the query.
摘要翻译：一种用于管理数据的方法包括识别在已经更新的一个或多个计算机上执行的归档文件系统的节点，获取归档文件系统内的时间排序节点状态改变事件，存储节点状态改变事件以及读取所存储的节点状态改变事件该方法还包括获取包含在已被更新的节点内的当前信息，更新包含在一个或多个计算机上执行的数据库系统中的数据，以反映获取的信息，查询数据库系统以及在归档文件系统上执行数据策略基于查询的结果。

33. 发明申请

US20100306165A1 RADIO FREQUENCY MICROSCOPE FOR AMPLIFYING AND ANALYZING ELECTROMAGNETIC SIGNALS 有权
标题翻译：用于放大和分析电磁信号的无线电频率显微镜
公开(公告)号：US20100306165A1
公开(公告)日：2010-12-02
申请号：US12473173
申请日：2009-05-27
申请人： Kenny C. Gross , Ramakrishna C. Dhanekula , David K. McElfresh
发明人： Kenny C. Gross , Ramakrishna C. Dhanekula , David K. McElfresh
IPC分类号： G06N5/02 , G01R29/08
CPC分类号： G01R29/0871 , G01R31/308
摘要： One embodiment provides a technique for analyzing a target electromagnetic signal radiating from a monitored system. During the technique, the monitored system is positioned at a first locus of an ellipsoidal surface to amplify the target electromagnetic signal received at a second locus of the ellipsoidal surface. Next, the amplified target electromagnetic signal is monitored using an antenna positioned at the second locus of the ellipsoidal surface. Finally, the integrity of the monitored system is assessed by analyzing the amplified target electromagnetic signal monitored by the antenna.
摘要翻译：一个实施例提供了一种用于分析从被监视系统辐射的目标电磁信号的技术。在该技术期间，所监视的系统位于椭圆面的第一轨迹处，以放大在椭圆面的第二轨迹处接收到的目标电磁信号。接下来，使用位于椭圆面的第二轨迹处的天线来监视放大的目标电磁信号。最后，通过分析由天线监测的放大的目标电磁信号来评估监控系统的完整性。

34. 发明申请

US20100292959A1 Telemetry data analysis using multivariate sequential probability ratio test 有权
标题翻译：遥测数据分析采用多元顺序概率比测试
公开(公告)号：US20100292959A1
公开(公告)日：2010-11-18
申请号：US12454226
申请日：2009-05-14
申请人： Kenny C. Gross , Ramakrishna C. Dhanekula , Aleksey M. Urmanov
发明人： Kenny C. Gross , Ramakrishna C. Dhanekula , Aleksey M. Urmanov
IPC分类号： G06F17/18 , G06F15/00
CPC分类号： G06F11/3447 , G06F11/0724 , G06F11/0748 , G06F11/0754 , G06F11/141 , G06F11/3058 , G06F11/3072 , G06F11/3452 , G06F2201/81 , G06F2201/88
摘要： One embodiment provides a system that analyzes telemetry data from a monitored system. During operation, the system periodically obtains the telemetry data as a set of telemetry variables from the monitored system and updates a multidimensional real-time distribution of the telemetry data using the obtained telemetry variables. Next, the system analyzes a statistical deviation of the multidimensional real-time distribution from a multidimensional reference distribution for the monitored system using a multivariate sequential probability ratio test (SPRT) and assesses the integrity of the monitored system based on the statistical deviation of the multidimensional real-time distribution. If the assessed integrity falls below a threshold, the system determines a fault in the monitored system corresponding to a source of the statistical deviation.
摘要翻译：一个实施例提供了一种从被监控系统分析遥测数据的系统。在操作期间，系统周期性地将遥测数据作为来自被监视系统的一组遥测变量获得，并使用获得的遥测变量更新遥测数据的多维实时分布。接下来，系统使用多变量连续概率比测试（SPRT）分析所监视系统的多维参考分布的多维实时分布的统计偏差，并且基于多维度的统计偏差来评估所监视系统的完整性实时分配。如果评估的完整性低于阈值，则系统确定对应于统计偏差来源的被监视系统中的故障。

35. 发明申请

US20100287516A1 METHODS AND SYSTEM FOR SELECTING GATE SIZES, REPEATER LOCATIONS, AND REPEATER SIZES OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于选择集成电路的栅极尺寸，重复位置和重复尺寸的方法和系统
公开(公告)号：US20100287516A1
公开(公告)日：2010-11-11
申请号：US12437174
申请日：2009-05-07
申请人： Salim U. Chowdhury
发明人： Salim U. Chowdhury
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendant gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.
摘要翻译：一种用于选择集成电路的逻辑网络的栅极尺寸的方法，其中所述逻辑网络由包括节点，栅极和互连件的多个逻辑路径定义，包括在一个或多个计算机处将栅极尺寸分配给与其相邻的栅极逻辑网络的定时路径端节点，基于门和互连延迟模型确定每个分配的门尺寸的性能/负载参数的n元组，以及确定两个或多个逻辑路径是否共享后代门。共享后代门的两个或多个逻辑路径被耦合。该方法还包括基于共享后代门的栅极大小，逐个递归地传播耦合的逻辑路径的n个元组，将沿着耦合逻辑路径的n元组的元组分组，检测是否基于对二进制对参数的n元组的比较，并且消除所有耦合的逻辑路径中n个元组的任何一个n个元组，沿着耦合的修剪与次佳箱相关的门尺寸的逻辑路径。

36. 发明申请

US20100286974A1 TECHNIQUE USING POWER MACROMODELING FOR REGISTER TRANSFER LEVEL POWER ESTIMATION 有权
标题翻译：使用功率MACROMODELING进行寄存器传输电平估计的技术
公开(公告)号：US20100286974A1
公开(公告)日：2010-11-11
申请号：US12436019
申请日：2009-05-05
申请人： Krishnan Sundaresan , Pravin Chander Chandran
发明人： Krishnan Sundaresan , Pravin Chander Chandran
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.
摘要翻译：一种用于估计集成电路的设计块的功耗的方法包括从旧式微处理器的设计中获得功耗数据，选择一组功耗参数，对所选择的所获得的功耗数据应用曲线拟合技术一组功耗参数，基于曲线拟合技术和一个或多个功耗参数创建新的功耗模型，使用新一代微处理器的寄存器传输级别的模型来表示寄存器传输级别的估计新一代微处理器的功耗，并基于该模型输出寄存器传输级功耗估计。

37. 发明申请

US20100280651A1 DATA CARTRIDGE AND TAPE LIBRARY INCLUDING FLASH MEMORY 审中-公开
标题翻译：数据盒和磁带库包括闪存
公开(公告)号：US20100280651A1
公开(公告)日：2010-11-04
申请号：US12433307
申请日：2009-04-30
申请人： Dwayne A. Edling , Mark L. Watson
发明人： Dwayne A. Edling , Mark L. Watson
IPC分类号： G06F7/00 , G06F12/00 , G06F12/14
CPC分类号： G06F3/0649 , G06F3/061 , G06F3/0686 , G11B15/6835 , G11B23/042 , G11B27/002 , G11B2220/41 , G11B2220/655
摘要： A data storage system for use with a plurality of tape cartridges is provided. Each tape cartridge includes a length of tape media and an amount of flash memory. The data storage system includes a tape cartridge library having a plurality of storage cells. Each storage cell is configured to store a tape cartridge. The tape cartridge library further includes a plurality of tape drives. Each tape drive is configured to access a tape cartridge when the tape cartridge is received in the tape drive. The system further includes a robotic tape mover and a flash memory access mechanism. The robotic tape mover moves tape cartridges between the plurality of storage cells and the plurality of tape drives. The flash memory access mechanism is configured in the tape cartridge library to access the flash memory of a tape cartridge when the tape cartridge is in the tape cartridge library.
摘要翻译：提供了一种用于多个磁带盒的数据存储系统。每个磁带盒包括一定长度的磁带介质和一定量的闪存。数据存储系统包括具有多个存储单元的带盒库。每个存储单元被配置为存储磁带盒。带盒库还包括多个磁带驱动器。每个磁带驱动器都配置为在磁带驱动器中接收磁带时访问磁带盒。该系统还包括机器人磁带机和闪存存取机构。机器人磁带移动器在多个存储单元和多个磁带驱动器之间移动磁带盒。当磁带盒位于磁带库中时，闪存存取存取机构配置在磁带库中，以访问磁带盒的闪存。

38. 发明申请

US20100271085A1 DELAY CHAIN INITIALIZATION 有权
标题翻译：延迟链初始化
公开(公告)号：US20100271085A1
公开(公告)日：2010-10-28
申请号：US12430846
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03L7/00
CPC分类号： H03K5/131
摘要： A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
摘要翻译：延迟链初始化电路，其将单面信号转换为双面信号。双面延迟链包括数据轨和互补轨。数据轨道和数据补充轨道中的每一条都包括通过交叉耦合的逆变器对互连的逆变器链。延迟链初始化电路适于在输出端产生基本同时的数据信号和数据补码信号。

39. 发明申请

US20100250831A1 DATA STORAGE SYSTEM MANAGER AND METHOD FOR MANAGING A DATA STORAGE SYSTEM 有权
标题翻译：用于管理数据存储系统的数据存储系统管理器和方法
公开(公告)号：US20100250831A1
公开(公告)日：2010-09-30
申请号：US12414121
申请日：2009-03-30
申请人： John Timothy O'Brien , Michael Steven Milillo , Carl Thomas Madison, JR.
发明人： John Timothy O'Brien , Michael Steven Milillo , Carl Thomas Madison, JR.
IPC分类号： G06F12/00 , G06F12/16 , G06F12/02
CPC分类号： G06F11/3433 , G06F11/1662 , G06F11/202 , G06F11/2094 , G06F2201/87 , G06F2201/885
摘要： A data storage system manager includes one or more servers, at least one data collector deployed on at least one of the servers, at least one policy engine deployed on at least one of the servers, and at least one configuration manager deployed on at least one the servers. The at least one data collector is configured to collect resource utilization information including data storage wear rate of data storage system data storage modules. The at least one policy engine is configured to evaluate the collected information and to initiate changes to a configuration of the data storage system based on data storage wear rate and work load distribution policies. The at least one configuration manager is configured to implement the changes initiated by the at least one policy engine to control the data storage wear rate and a skew of the work load distribution within the data storage system.
摘要翻译：数据存储系统管理器包括一个或多个服务器，部署在至少一个服务器上的至少一个数据收集器，部署在至少一个服务器上的至少一个策略引擎，以及部署在至少一个服务器上的至少一个配置管理器服务器。所述至少一个数据收集器被配置为收集包括数据存储系统数据存储模块的数据存储磨损率的资源利用信息。所述至少一个策略引擎被配置为基于数据存储磨损率和工作负载分配策略来评估所收集的信息并且启动对所述数据存储系统的配置的改变。至少一个配置管理器被配置为实现由至少一个策略引擎启动的改变，以控制数据存储磨损率和数据存储系统内的工作负载分布的偏斜。

40. 发明申请

US20100247029A1 THERMAL TUNING OF AN OPTICAL DEVICE 有权
标题翻译：光学装置的热调谐
公开(公告)号：US20100247029A1
公开(公告)日：2010-09-30
申请号：US12415882
申请日：2009-03-31
申请人： Guoliang Li , Ashok V. Krishnamoorthy , John E. Cunningham , Ivan Shubin , Xuezhe Zheng
发明人： Guoliang Li , Ashok V. Krishnamoorthy , John E. Cunningham , Ivan Shubin , Xuezhe Zheng
IPC分类号： G02B6/12
CPC分类号： G02B6/12007 , G02B2006/12061 , G02F1/011 , G02F1/0147 , G02F2202/10
摘要： Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide with a high thermal resistance to the surrounding external environment and a low thermal resistance to a localized heater. In particular, the thermal resistances associated with thermal dissipation paths from a heater in the optical device to an external environment via electrodes and via the substrate are increased, while the thermal resistance between the optical waveguide and the heater is decreased.
摘要翻译：描述了光学器件，光学器件阵列以及用于制造光学器件或阵列的技术的实施例。该光学器件实现在基板（例如硅）上，并且包括具有对周围外部环境的高耐热性和对局部加热器的低热阻的热可调谐光波导。特别地，与通过电极和经由基板的从光学装置中的加热器到外部环境的热耗散路径相关联的热阻增加，同时光波导和加热器之间的热阻降低。

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