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31. 发明申请

US20150357999A1 Direct Coupled Biasing Circuit for High Frequency Applications 有权
标题翻译：直接耦合偏置电路用于高频应用
公开(公告)号：US20150357999A1
公开(公告)日：2015-12-10
申请号：US14828955
申请日：2015-08-18
申请人： TENSORCOM, INC.
发明人： Zaw Soe , KhongMeng Tham
IPC分类号： H03K3/012 , H01Q1/50 , H03K17/56
CPC分类号： H03K3/012 , G05F3/16 , H01Q1/50 , H03K17/56 , H04B5/0075
摘要： This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.
摘要翻译：当设计高频（〜60GHz）电路时，本发明消除了对“电容器耦合”或“变压器耦合”的需求以及与这些耦合技术相关联的不期望的寄生电容和电感。在这个频率下，两个相邻阶段之间的距离需要最小化。与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。该谐振电路的引入允许使用金属迹线将第一级“直接耦合”到下一级。 “直接耦合”技术将高频信号和偏置电压都通过下一级。与“交流耦合”或“变压器耦合”方法相比，“直接耦合”方法克服了大的管芯面积使用，因为既不需要电容器也不需要变压器来在级之间传输高频信号。

32. 发明授权

US08873339B2 Method and apparatus for a clock and signal distribution network for a 60 GHz transmitter system 有权
标题翻译：用于60 GHz发射机系统的时钟和信号分配网络的方法和装置
公开(公告)号：US08873339B2
公开(公告)日：2014-10-28
申请号：US13572519
申请日：2012-08-10
申请人： Jiashu Chen
发明人： Jiashu Chen
IPC分类号： H04B1/02 , H03B27/00 , G01S7/491 , G01S7/484 , G01S5/02
CPC分类号： H03B27/00 , G01S5/0226 , G01S7/484 , G01S7/4911 , G06F1/10 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H03K5/15
摘要： Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 μm) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.
摘要翻译：本文提出了一种用于波束成形系统的低功率裸片60GHz分布网络，可以随着发射机数量的增加而进行缩放。如果使用传输线形成，尺寸将与四分之一波长（〜600μm）成比例的传输线路功率分配器和正交混合器由电感器/电容器构成，并将面积减少80％以上。输入同相I时钟和输入正交Q时钟被组合成锁定同相I时钟和正交Q时钟之间的相位关系的单个复合时钟波形。复合时钟通过使用耦合在晶片表面上的源和目的位置的共平面波导（CPW）形成的单个传输线传输。一旦个体需要同相I和正交Q时钟，它们可以从复合时钟波形在目的地产生。

33. 发明授权

US08816786B2 Method and apparatus of a crystal oscillator with a noiseless and amplitude based start up control loop 有权
标题翻译：具有无噪声和振幅的启动控制回路的晶体振荡器的方法和装置
公开(公告)号：US08816786B2
公开(公告)日：2014-08-26
申请号：US13632173
申请日：2012-10-01
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham
IPC分类号： H03L5/00 , H03B5/36
CPC分类号： H03B5/364 , H03B5/06 , H03B2200/0088 , H03B2200/0094 , H03B2201/031 , H03L5/00
摘要： A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.
摘要翻译：使用大的增益快速启动晶体振荡。一旦振荡开始，就检测振幅。控制电路基于测量的幅度来确定禁用受控开关阵列中的低电阻路径，以将施加的增益降低到低于晶体的功率耗散规格。另一种技术引入了一种混合信号控制电源多路径电阻阵列，可以调整晶体的最大电流。逐次逼近寄存器将振幅转换成几个分区，并使能/禁用振荡器的反相器的几个电源路由路径之一。这允许由客户选择的晶体和片上驱动电路之间更好地匹配，以在不强调晶体的情况下加电振荡器。通过在三极管区域中操作晶体管而不是线性区域来使振荡器电路的“l / f”噪声最小化。

34. 发明授权

US08680899B2 High performance divider using feed forward, clock amplification and series peaking inductors 有权
标题翻译：高性能分频器采用前馈，时钟放大和串联峰值电感
公开(公告)号：US08680899B2
公开(公告)日：2014-03-25
申请号：US13243908
申请日：2011-09-23
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H03B19/00
CPC分类号： H03K21/023 , H03L7/193
摘要： A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.
摘要翻译：锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

35. 发明申请

US20140043104A1 Method and Apparatus for a Clock and Signal Distribution Network for a 60 GHz Transmitter System 有权
标题翻译：用于60 GHz发射机系统的时钟和信号分配网络的方法和装置
公开(公告)号：US20140043104A1
公开(公告)日：2014-02-13
申请号：US13572519
申请日：2012-08-10
申请人： Jiashu Chen
发明人： Jiashu Chen
IPC分类号： H03K3/03
CPC分类号： H03B27/00 , G01S5/0226 , G01S7/484 , G01S7/4911 , G06F1/10 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H03K5/15
摘要： Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 μm) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.
摘要翻译：本文提出了一种用于波束成形系统的低功率裸片60GHz分布网络，可以随着发射机数量的增加而进行缩放。如果使用传输线形成尺寸将与四分之一波长（〜600μm）成比例的传输线路功率分配器和正交混合器由电感器/电容器构成，并将面积减少80％以上。输入同相I时钟和输入正交Q时钟被组合成锁定同相I时钟和正交Q时钟之间的相位关系的单个复合时钟波形。复合时钟通过使用耦合在晶片表面上的源和目的位置的共平面波导（CPW）形成的单个传输线传输。一旦个体需要同相I和正交Q时钟，它们可以从复合时钟波形在目的地产生。

36. 发明申请

US20140035667A1 Differential Source Follower having 6dB Gain with Applications to WiGig Baseband Filters 有权
标题翻译：差分源跟随器具有6dB增益，可应用于WiGig基带滤波器
公开(公告)号：US20140035667A1
公开(公告)日：2014-02-06
申请号：US14053189
申请日：2013-10-14
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H03H11/12 , H03H3/00
CPC分类号： H03H11/1217 , H03F3/195 , H03F3/301 , H03F3/45179 , H03F3/505 , H03F2203/45528 , H03F2203/45544 , H03F2203/45594 , H03H3/00
摘要： Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.
摘要翻译： Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器，以满足外部滤波器特性。本发明消除了对于稳定性的内部反馈路径的需要，并增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。源极跟随器提供6 dB的交流电压增益，并代替Sallen-Key滤波器中的运算放大器。 Sallen-Key滤波器需要差分配置，以产生所有需要的信号，并在前馈路径中使用这些信号。此外，由于源极跟随器仅使用两个n沟道堆叠器件，因此在40nm CMOS技术中1.2V电压源的裕量电压最大可达数百毫伏。因此，Sallen-Key滤波器所需的880 MHz带宽可以使用创新的源跟踪器轻松实现。

37. 发明授权

US08618891B2 Method and apparatus of a resonant oscillator separately driving two independent functions 有权
公开(公告)号：US08618891B2
公开(公告)日：2013-12-31
申请号：US13340790
申请日：2011-12-30
申请人： Syed Enam Rehman
发明人： Syed Enam Rehman
IPC分类号： H03B1/00
CPC分类号： H03L7/00 , H03B1/00 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/0062 , H03L1/023 , H03L7/18
摘要： Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

38. 发明申请

US20130169373A1 Method and Apparatus of Capacitively Coupling an Adjustable Capacitive Circuit in a VCO 审中-公开
标题翻译：在VCO中电容耦合可调电容电路的方法和装置
公开(公告)号：US20130169373A1
公开(公告)日：2013-07-04
申请号：US13340813
申请日：2011-12-30
申请人： Syed Enam Rehman
发明人： Syed Enam Rehman
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1243 , H03B5/1265 , H03B2200/0062 , H03L7/099 , H03L7/18 , H03L2207/06
摘要： Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.
摘要翻译： RCL谐振电路中的电容调整通常通过调整施加到电容器一侧的直流电压来进行。电容器的一侧通常连接到RCL谐振电路中的再生电路的输出节点或栅极。谐振电路的电容成为由谐振电路产生的直流电压和交流正弦信号的函数。通过电容耦合电容器的两个节点，DC电压可以在输出波形的全摆幅时控制电容器的值。此外，代替RCL谐振电路驱动负载输出的单个差分功能，每个输出驱动独立的单端功能; 从而提供两个同时的操作来代替一个差分功能。

39. 发明申请

US20130078933A1 Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60GHz Power Amplifier Circuits 有权
标题翻译：在60GHz功率放大器电路中最小化外部寄生电阻的方法和装置
公开(公告)号：US20130078933A1
公开(公告)日：2013-03-28
申请号：US13243986
申请日：2011-09-23
申请人： Zaw Soe
发明人： Zaw Soe
IPC分类号： H04W88/02 , H03B11/00
CPC分类号： H01Q11/12
摘要： Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
摘要翻译：超高频电路遭受寄生电阻。在60GHz，传统的布局技术可以在关键位置引入电路损耗。预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。此外，使用通孔堆叠的抽头点来修改互连的谐振特性。最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

40. 发明申请

US20120319673A1 Direct Coupled Biasing Circuit for High Frequency Applications 有权
标题翻译：直接耦合偏置电路用于高频应用
公开(公告)号：US20120319673A1
公开(公告)日：2012-12-20
申请号：US13163562
申请日：2011-06-17
申请人： KhongMeng Tham , Zaw Soe
发明人： KhongMeng Tham , Zaw Soe
IPC分类号： G05F3/02
CPC分类号： H03K3/012 , G05F3/16 , H01Q1/50 , H03K17/56 , H04B5/0075
摘要： This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.
摘要翻译：当设计高频（〜60GHz）电路时，本发明消除了对电容器耦合或变压器耦合的需要，以及与这些耦合技术相关联的不期望的寄生电容和电感。在这个频率下，两个相邻阶段之间的距离需要最小化。与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。该谐振电路的引入允许第一级使用金属迹线直接耦合到下一级。直接耦合技术将高频信号和偏置电压都通过下一级。与AC耦合或变压器耦合方法相比，直接耦合方法克服了大的管芯面积使用，因为电容器和变压器都不需要在级之间传输高频信号。

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