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31. 发明申请

US20140375364A1 FREQUENCY SYNTHESIS WITH GAPPER AND MULTI-MODULUS DIVIDER 有权
标题翻译：与GAPPER和MULTI-MODULUS DIVIDER的频率合成
公开(公告)号：US20140375364A1
公开(公告)日：2014-12-25
申请号：US14469456
申请日：2014-08-26
申请人： Applied Micro Circuits Corporation
发明人： Yehuda AZENKOT , Michael GROSNER , Timothy P. WALKER
IPC分类号： H03L7/16
CPC分类号： H03L7/06
摘要： Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.
摘要翻译：使用间隙和多模式分频器进行频率合成的系统和方法。频率合成器可以包括间隔器，多模式分频器和锁相环（PLL）。当输出信号的频率意图大于相应的输入信号时，可以由分频器借由分频器的因子，以产生大于1的有理分频比G，以使分频器能够执行由G.的分频。PLL能够乘以来自第一整数分频器的有间隙信号输出，并从有间隙信号衰减抖动。

32. 发明授权

US08912857B2 PLL system and method for controlling a gain of a VCO circuit 有权
标题翻译： PLL系统和控制VCO电路增益的方法
公开(公告)号：US08912857B2
公开(公告)日：2014-12-16
申请号：US12936214
申请日：2008-04-18
申请人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
发明人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
IPC分类号： H03B5/12 , H03L7/16 , H03L7/099 , H03L7/113 , H03L7/18
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译：一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。

33. 发明申请

US20140340129A1 FREQUENCY CONTROL SYSTEM WITH DUAL-INPUT BIAS GENERATOR TO SEPARATELY RECEIVE MANAGEMENT AND OPERATIONAL CONTROLS 有权
标题翻译：具有双输入偏置发电机的频率控制系统，以分别接收管理和运行控制
公开(公告)号：US20140340129A1
公开(公告)日：2014-11-20
申请号：US13977424
申请日：2012-04-13
申请人： Atul Maheshwari , Parker J. Rachel , Kuan-Yueh James Shen
发明人： Atul Maheshwari , Parker J. Rachel , Kuan-Yueh James Shen
IPC分类号： H03L7/16 , H03L7/08
CPC分类号： H03L7/16 , H03L7/0802 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/099 , H03L7/1072 , H03L2207/06
摘要： Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.
摘要翻译：控制相对于参考频率的输出频率的方法和系统。频率控制系统包括双输入偏置发生器，用于分别接收管理和操作控制。偏置发生器包括：第一偏置发生器电路，用于在第一操作模式期间基于管理控制和偏置反馈参考之间的差异产生偏置控制;第二偏置发生器电路，用于基于第一偏置发生器电路之间的差产生偏置控制; 在第二操作模式期间的操作控制和偏置反馈参考，以及偏置反馈参考电路，以基于偏置控制产生偏置反馈参考。第一模式可以包括表征和/或启动模式。第二模式可以包括诸如反馈控制模式的操作模式。

34. 发明授权

US08890595B2 Dynamic clock phase control architecture for frequency synthesis 有权
标题翻译：用于频率合成的动态时钟相位控制架构
公开(公告)号：US08890595B2
公开(公告)日：2014-11-18
申请号：US13895849
申请日：2013-05-16
申请人： Fmax Technologies, Inc.
发明人： Iain Ross Mactaggart
IPC分类号： H03K3/00 , H03H11/16 , H03K5/13 , H03L7/16
CPC分类号： H03L7/16 , G06F1/025 , H03K5/13
摘要： Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
摘要翻译：实现具有减少的模拟组件的数字控制振荡器的装置和电路的实施例。在一个示例中，数字控制振荡器可以包括由失速电路控制的相位累加器，以选择性地停止相位累加器。在一些示例中，数控振荡器可以包括基于相位累加器的输出来选择相位选择电路的多个相位的相位选择电路。在一些示例中，这些选择的相位然后可以由相位内插器使用以产生合成时钟信号。

35. 发明授权

US08810286B1 Method and apparatus for synthesizing a low phase noise frequency with wide tuning range 有权
标题翻译：用于合成具有宽调谐范围的低相位噪声频率的方法和装置
公开(公告)号：US08810286B1
公开(公告)日：2014-08-19
申请号：US13875829
申请日：2013-05-02
申请人： MStar Semiconductor, Inc.
发明人： Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03K19/082 , H03K19/094 , H03L7/16
CPC分类号： H03L7/16
摘要： Direct digital frequency synthesis is the process by which a digital frequency synthesizer component may output a stable, precise clock frequency at any of a broad range of possible frequency output values for any number of applications, usually across an integrated circuit. The digital frequency synthesizer set forth in this disclosure is a combination of a controller configured to receive a frequency control word and generate a first frequency control sub-word and a second frequency control sub-word based on the frequency control word, a frequency generator configured to generate a source frequency within a first predetermined frequency range based on the first frequency control sub-word, and a variable frequency divider configured to generate an output frequency within a second predetermined range based on the second frequency control sub-word and the source frequency.
摘要翻译：直接数字频率合成是数字频率合成器组件可以在通常跨集成电路的任何数量的应用的可能的频率输出值的任何范围内输出稳定，精确的时钟频率的过程。本公开中提出的数字频率合成器是被配置为接收频率控制字并基于频率控制字产生第一频率控制子字和第二频率控制子字的控制器的组合，频率发生器被配置基于第一频率控制子字，在第一预定频率范围内产生源频率，以及可变分频器，其被配置为基于第二频率控制子字和源频率在第二预定范围内生成输出频率。

36. 发明申请

US20140176245A1 OSCILLATOR AND SELF-CALIBRATION METHOD THEREOF 有权
标题翻译：振荡器及其自校准方法
公开(公告)号：US20140176245A1
公开(公告)日：2014-06-26
申请号：US14032925
申请日：2013-09-20
申请人： Grace Semiconductor Manufacturing Corporation
发明人： Ada Chen , Emir Yu
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03L1/00 , H03L7/00 , H03L7/093
摘要： An oscillator and a self-calibration method thereof are provided. The oscillator includes: an oscillation unit for generating an oscillation signal; a converting unit for converting frequency of the oscillation signal into a voltage signal; a comparison unit for comparing the voltage signal with a first voltage corresponding to a higher frequency and a second voltage corresponding to a lower frequency, and outputting a comparison result signal; an adjusting unit for storing a calibration value, adjusting the calibration value based on the comparison result signal and outputting a calibration signal corresponding to the adjusted calibration value; and a calibration unit for calibrating the frequency of the oscillation signal based on the calibration signal. Self-calibration for the frequency of the oscillation signal may be achieved, which may ensure the stability of the frequency of the oscillation signal.
摘要翻译：提供振荡器及其自校准方法。振荡器包括：用于产生振荡信号的振荡单元; 转换单元，用于将振荡信号的频率转换成电压信号; 比较单元，用于将电压信号与对应于较低频率的较高频率和第二电压对应的第一电压进行比较，并输出比较结果信号; 调整单元，用于存储校准值，基于比较结果信号调整校准值，并输出与校准校准值对应的校准信号; 以及校准单元，用于基于校准信号来校准振荡信号的频率。可以实现对振荡信号频率的自校准，这可以确保振荡信号的频率的稳定性。

37. 发明申请

US20140091865A1 OSCILLATION CIRCUIT, ELECTRONIC APPARATUS, AND MOVING OBJECT 有权
标题翻译：振荡电路，电子设备和移动对象
公开(公告)号：US20140091865A1
公开(公告)日：2014-04-03
申请号：US14034934
申请日：2013-09-24
申请人： Seiko Epson Corporation
发明人： Masayuki ISHIKAWA , Takehiro YAMAMOTO , Yosuke ITASAKA
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03B1/00 , H03B5/36 , H03B5/364 , H03L1/023
摘要： An oscillation circuit is connected to a resonator element (crystal resonator) and oscillates a resonator element to output an oscillation signal. The oscillation circuit includes an amplification element (inverter), and a set of variable capacitive elements having at least two variable capacitive elements, which are connected to an oscillation loop from an output to an input of the amplification element and the capacitance values thereof are controlled with potential differences between reference voltages and a variable control voltage. In each variable capacitive element of a set of variable capacitive elements, the common control voltage is applied to one terminal, and the reference voltage which differs between the variable capacitive elements is input to the other terminal.
摘要翻译：振荡电路连接到谐振器元件（晶体谐振器），并振荡谐振元件以输出振荡信号。振荡电路包括放大元件（反相器），并且具有至少两个可变电容元件的可变电容元件组被连接到从放大元件的输出到输入端的振荡回路及其电容值具有参考电压和可变控制电压之间的潜在差异。在一组可变电容元件的每个可变电容元件中，公共控制电压被施加到一个端子，并且在可变电容元件之间不同的参考电压被输入到另一个端子。

38. 发明授权

US08248175B2 Oscillator with external voltage control and interpolative divider in the output path 有权
标题翻译：具有外部电压控制的振荡器和输出路径中的内插分压器
公开(公告)号：US08248175B2
公开(公告)日：2012-08-21
申请号：US12981854
申请日：2010-12-30
申请人： Susumu Hara
发明人： Susumu Hara
IPC分类号： H03B1/00 , H03B5/00 , H03B19/00 , H03L7/00 , H03L7/16 , H03L7/18
CPC分类号： H03L7/16 , G06F1/08
摘要： An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.
摘要翻译：使用内插分压器作为频率调制器，从外部电压控制端子控制振荡器输出。振荡器包括参考时钟发生器，模数转换器和内插分压器。标称输出频率由参考时钟的频率和内插分频器的额定分频值决定。分频值根据经由模数转换器转换为数字值的电压控制输入值而改变。多个内插分频器可以耦合到单个参考时钟发生器，并且每个具有电压控制输入和模数转换器。

39. 发明申请

US20080290953A1 System and Method for Generating LO Frequencies with Phase Locking in 2 Steps 有权
标题翻译：用2阶段锁相生成LO频率的系统和方法
公开(公告)号：US20080290953A1
公开(公告)日：2008-11-27
申请号：US11753999
申请日：2007-05-25
申请人： Christoph Sandner , Staffan Ek , Stefano Marsili
发明人： Christoph Sandner , Staffan Ek , Stefano Marsili
IPC分类号： H03L7/16 , H03L7/08
CPC分类号： H03L7/23 , H04B1/7136 , H04B2001/71362 , H04B2001/71365 , H04L2027/0016 , H04L2027/0057 , H04L2027/0065
摘要： System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal.
摘要翻译：用于产生多个本地振荡器信号的系统和方法，包括具有用于接收第一参考信号输入并具有传输第二参考信号的输出的输入的第一级锁相环（PLL），其中所述第二参考信号是整数或第一参考信号的分数倍; 和多个第二级PLL，每个第二级PLL具有耦合到第一级PLL的输出并接收第二参考信号的输入，并且每个第二级PLL具有用于发送本地振荡器信号的输出，其中每个本地振荡器信号是第二参考信号的整数倍。

40. 发明申请

US20080218281A1 Anodically Bonded Cell, Method for Making Same and Systems Incorporating Same 审中-公开
标题翻译：阳极粘结电池，制造相同的方法和包含相同的系统
公开(公告)号：US20080218281A1
公开(公告)日：2008-09-11
申请号：US12121876
申请日：2008-05-16
申请人： Steven Alan Lipp , Joseph H. Abeles , Alan Michael Braun , Sterling Eduard McBride , John P. Riganati , Ralph Doud Whaley , Peter J. Zanzucchi
发明人： Steven Alan Lipp , Joseph H. Abeles , Alan Michael Braun , Sterling Eduard McBride , John P. Riganati , Ralph Doud Whaley , Peter J. Zanzucchi
IPC分类号： H01S1/06 , H03L7/16 , H01L21/30
CPC分类号： G04F5/14
摘要： A cell suitable for use with an atomic clock and a method for making the same, the cell including: a silicon wafer having a recess formed therein; at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon sealing the recess; and, an alkali metal containing component and buffer gas contained in the recess. The method includes: providing a silicon wafer; forming a cavity through the silicon wafer; introducing an alkali metal containing component and buffer gas into the cavity; and, anodically bonding at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon to the wafer to close the cavity.
摘要翻译：适用于原子钟的电池及其制造方法，所述电池包括：形成有凹部的硅晶片; 至少一种无定形硅酸盐部件，其离子迁移率和温度膨胀系数近似于密封凹部的硅的非晶硅酸盐部件; 以及包含在所述凹部中的含碱金属成分和缓冲气体。该方法包括：提供硅晶片; 通过硅晶片形成空腔; 将含碱金属的组分和缓冲气体引入所述空腔中; 并且将具有大约硅的离子迁移率和温度膨胀系数的至少一种无定形硅酸盐构件阳极结合到晶片上以封闭空腔。

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