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    • 31. 发明授权
    • Drop-out detecting circuit
    • 掉电检测电路
    • US5418656A
    • 1995-05-23
    • US972174
    • 1992-11-04
    • Hiromi FukazawaMasahiro Ikeda
    • Hiromi FukazawaMasahiro Ikeda
    • G11B20/18H04N5/94
    • H04N5/94G11B20/18
    • To set the drop-out detection level constant in the drop-out detecting circuit used for a magnetic recording apparatus, without regulating the output level of a magnetic recording head and the gain of a preamplifier, the detecting circuit comprises an envelope detection section for detecting the envelope of a reproduced signal; a voltage division section for dividing the output signal voltage of the envelope detection section; and a comparator for comparing the output signal of the voltage division section with the reproduced signal to detect a drop-out of the reproduced signal. Therefore, it is possible to reduce the number of parts and the number of adjustment process to reduce the manufacturing cost thereof. Further, to detect the drop-out portion throughout as defective tape locations, irrespective of the length of the drop-out portion, the detecting circuit further comprises a drop-out start detection section, a drop-out end detection section, and an OR gate.
    • 为了在用于磁记录装置的脱出检测电路中设定脱出检测电平的常数,而不调节磁记录头的输出电平和前置放大器的增益,检测电路包括用于检测 再生信号的包络; 分压部,其对所述包络检测部的输出信号电压进行分压; 以及比较器,用于将分压部分的输出信号与再现信号进行比较,以检测再现信号的退出。 因此,可以减少部件的数量和调整过程的数量,以降低其制造成本。 此外,为了检测作为有缺陷的磁带位置的丢失部分,与检出电路的长度无关,检测电路还包括一个出口开始检测部分,一个退出结束检测部分和一个OR 门。
    • 32. 发明授权
    • Concealing method of video signal
    • 视频信号隐藏方法
    • US5416600A
    • 1995-05-16
    • US291460
    • 1994-08-17
    • Chiyoko MatsumiTatsuro Juri
    • Chiyoko MatsumiTatsuro Juri
    • H04N19/60H03M13/00H04N1/411H04N5/926H04N5/945H04N11/04H04N19/423H04N19/44H04N19/65H04N19/85H04N19/89H04N19/895H04N5/94
    • H04N5/945H04N19/895H04N5/9261
    • A coded digital video signal is obtained by dividing a digital video signal into plural pages each composed of K fields of pixel data, decomposing pixel data in each two pages into plural blocks each composed of a predetermined number of pixel data, and encoding the pixel data in each block by bit rate reduction encoding and error correction encoding. The thus obtained coded digital video signal is reproduced or transmitted and then subjected to a concealment process. The concealment process includes decoding the coded digital video signal to obtain reproduced blocks of pixel data and to detect an error block containing an error among the reproduced blocks, composing the reproduced blocks to obtain plural reproduced pages of pixel data, and concealing error pixel data contained in the error block in each two reproduced pages. Error pixel data in a first page is concealed using pixel data in a previous page, and error pixel data in a second page is concealed using pixel data in a succeeding page.
    • 通过将数字视频信号分割成由K个像素数据构成的多个页面来获得编码数字视频信号,将每两页中的像素数据分解为由预定数量的像素数据组成的多个块,并且对像素数据进行编码 在每个块中通过比特率降低编码和纠错编码。 如此获得的编码数字视频信号被再现或发送,然后进行隐蔽处理。 隐藏处理包括对编码的数字视频信号进行解码以获得再现的像素数据块,并且检测包含再现块中的错误的错误块,构成再现块以获得多个再现页面的像素数据,以及隐藏包含的错误像素数据 在每两个重现页面的错误块中。 使用前一页中的像素数据隐藏第一页中的错误像素数据,并且使用后续页面中的像素数据隐藏第二页中的误差像素数据。
    • 33. 发明授权
    • Digital VCR signal processing apparatus for concealing uncorrectable
errors
    • 用于隐藏不可校正错误的数字VCR信号处理装置
    • US5392129A
    • 1995-02-21
    • US83052
    • 1993-06-25
    • Hideki OhtakaTatsuro Juri
    • Hideki OhtakaTatsuro Juri
    • G11B20/18G06T9/00H03M7/40H03M13/00H04N1/41H04N1/415H04N5/92H04N5/926H04N5/945H04N19/102H04N19/132H04N19/166H04N19/174H04N19/186H04N19/189H04N19/423H04N19/46H04N19/59H04N19/60H04N19/625H04N19/65H04N19/67H04N19/70H04N19/85H04N19/89H04N19/895H04N19/91H04N5/94
    • H04N5/945H04N19/895H04N5/9264
    • A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing digital signal presented in sync blocks is disclosed. Each sync block has a fixed area for low frequency data and five subsequent sync blocks define a sharing group for sharing high frequency data. The signal processing apparatus includes an inner and outer correction circuit for correcting errors in the sync blocks. An error flag is provided to a sync block which still has an error remaining after the processing in the correction circuit. A memory is provided for storing errorless sync blocks of one frame. A substitution switch is provided for passing the errorless sync blocks, but substituting a sync block stored in the memory for a sync block still having some errors. Five sync blocks produced from the substitution switch are held in a delay. When no substitute sync block is detected in the five sync blocks in the delay, the data in the five sync blocks are decoded by a bit rate reduction decoder. But, when one to four substitute sync block is detected in the five sync blocks in the delay, only the low frequency data of the five sync blocks in the fixed area are decoded by the bit rate reduction decoder.
    • 公开了一种用于再现同步块中呈现的数字信号的数字视频信号再现装置中的信号处理装置。 每个同步块具有用于低频数据的固定区域,并且五个后续同步块定义用于共享高频数据的共享组。 信号处理装置包括用于校正同步块中的错误的内部和外部校正电路。 错误标志被提供给在校正电路中的处理之后仍然具有错误的同步块。 提供存储器用于存储一帧的无错同步块。 提供了用于传递无错同步块的替代开关,但是将存储在存储器中的同步块替换为仍然具有一些错误的同步块。 由替代开关产生的五个同步块被延迟。 当延迟中的五个同步块中没有检测到替代同步块时,五个同步块中的数据被比特率降低解码器解码。 但是,当延迟中的五个同步块中检测到一到四个替代同步块时,只有固定区域中的5个同步块的低频数据被比特率降低解码器解码。
    • 34. 发明授权
    • Signal demodulation device
    • 信号解调装置
    • US5287197A
    • 1994-02-15
    • US685673
    • 1991-04-16
    • Koichi Sato
    • Koichi Sato
    • H04L27/233H04N9/88H04N5/94
    • H04L27/2334
    • A signal demodulation device includes a change point sensing circuit which senses a change point of an envelope of a DPSK signal, and a range setting circuit which generates a gate pulse corresponding to a period in which the DPSK signal cannot be changed. An output signal of the change point sensing circuit and the gate pulse are inputted to an AND gate so that a trigger prohibition signal is obtained. The trigger prohibition signal and the output signal of the change point sensing circuit are inputted to a NOR gate so that a trigger pulse corresponding only to a normal change point of the DPSK signal is generated, so that DPSK modulation data is obtained.
    • 信号解调装置包括感测DPSK信号的包络的变化点的变化点感测电路以及与DPSK信号不能改变的周期相对应地生成门脉冲的量程设定电路。 改变点检测电路和门脉冲的输出信号被输入到与门,从而获得触发禁止信号。 触发禁止信号和变化点感测电路的输出信号被输入到或非门,使得仅产生与DPSK信号的正常变化点对应的触发脉冲,从而获得DPSK调制数据。
    • 40. 发明授权
    • Dropout detecting circuit with one-half wavelength delay
    • 具有半波长延迟的压差检测电路
    • US4977461A
    • 1990-12-11
    • US323894
    • 1989-03-15
    • Isao Ichimura
    • Isao Ichimura
    • G11B7/00G11B7/004G11B20/02G11B20/06H04N5/94
    • G11B20/025H04N5/94
    • A dropout detection circuit includes a delay circuit for causing a delay in playback signals reproduced from an optical recording medium. The delay corresponds to one half of the wavelength of the central frequency of the carrier wave for the playback signals. A summation circuit sums the playback signals with the delayed output signals of the delay circuit, and a level detection circuit detects when the output signal level of the summation circuit exceeds a predetermined level. The output signal of the level detection circuit serves as a signal for detecting dropouts in the reproduced signals and is used as a control signal to control the operation of a switch. The switch normally passes demodulated playback signals to an output terminal. However, in case a dropout is detected in a given horizontal line, the control signal operates the switch so that it passes to the output terminal demodulated playback signals that have been delayed by one horizontal line period.
    • 一个压差检测电路包括延迟电路,用于引起从光学记录介质再现的重放信号的延迟。 延迟对应于重放信号的载波的中心频率的波长的一半。 求和电路将回放信号与延迟电路的延迟输出信号相加,电平检测电路检测何时加法电路的输出信号电平超过预定电平。 电平检测电路的输出信号用作检测再现信号中的丢失的信号,并用作控制信号以控制开关的操作。 开关通常将解调的重放信号传送到输出端子。 然而,在给定水平线中检测到压差的情况下,控制信号操作开关,使得其转到延迟了一个水平行周期的输出端解调的重放信号。