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31. 发明授权

US09070688B2 Method of patterning a semiconductor device having improved spacing and shape control and a semiconductor device 有权
标题翻译：图案化具有改进的间隔和形状控制的半导体器件的方法和半导体器件
公开(公告)号：US09070688B2
公开(公告)日：2015-06-30
申请号：US14053973
申请日：2013-10-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jhun Hua Chen , Yu-Lung Tung , Chi-Tien Chen , Hua-Tai Lin , Hsiang-Lin Chen , Hung-Chang Hsieh , Yi-Fan Chen
IPC分类号： H01L21/8242 , H01L23/528 , H01L21/8238 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76897 , H01L21/8238 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm−1.
摘要翻译：半导体器件包括半导体衬底，半导体衬底中的第一有源区和半导体衬底中的第二有源区。所述半导体器件还包括在所述半导体衬底之上的与所述第一有源区电连接并且具有与所述第二有源区相邻的第一端面的第一导电线，并且所述第一端面的图像对数斜率大于15μm-1 。

32. 发明授权

US09059256B2 Method for producing a controllable semiconductor component 有权
标题翻译：用于制造可控半导体部件的方法
公开(公告)号：US09059256B2
公开(公告)日：2015-06-16
申请号：US13614076
申请日：2012-09-13
申请人： Andreas Meiser , Markus Zundel
发明人： Andreas Meiser , Markus Zundel
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/76 , H01L21/311 , H01L21/768 , H01L21/28 , H01L23/48 , H01L21/74 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28008 , H01L21/28229 , H01L21/743 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L29/1095 , H01L29/401 , H01L29/407 , H01L29/4236 , H01L29/4916 , H01L29/495 , H01L29/51 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for producing a controllable semiconductor component. In a semiconductor body with a top side and a bottom side, a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body are formed in a common etching process. The first trench has a first width and the second trench has a second width greater than the first width. Then, in a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. Subsequently, the oxide layer is removed from the first trench completely or at least partly such that the semiconductor body comprises an exposed first surface area arranged in the first trench.
摘要翻译：公开了一种制造可控半导体部件的方法。在具有顶侧和底侧的半导体本体中，在公共蚀刻工艺中形成从顶侧突出到半导体本体的第一沟槽和从顶侧突出到半导体本体中的第二沟槽。第一沟槽具有第一宽度，第二沟槽具有大于第一宽度的第二宽度。然后，在共同的工艺中，在第一沟槽和第二沟槽中形成氧化物层，使得氧化物层填充第一沟槽并使第二沟槽的表面电绝缘。随后，完全或至少部分地从第一沟槽去除氧化物层，使得半导体主体包括布置在第一沟槽中的暴露的第一表面区域。

33. 发明授权

US09012984B2 Field effect transistor devices with regrown p-layers 有权
标题翻译：具有再生长p层的场效应晶体管器件
公开(公告)号：US09012984B2
公开(公告)日：2015-04-21
申请号：US13798919
申请日：2013-03-13
申请人： Cree, Inc.
发明人： Lin Cheng , Anant Agarwal , John Palmour
IPC分类号： H01L21/8242 , H01L29/66 , H01L29/78 , H01L27/06 , H01L29/739 , H01L29/06 , H01L29/16
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0653 , H01L29/1037 , H01L29/1095 , H01L29/1608 , H01L29/42376 , H01L29/66068 , H01L29/66666 , H01L29/7397 , H01L29/78 , H01L29/7811 , H01L29/7813
摘要： A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator.
摘要翻译：晶体管器件包括具有第一导电类型的漂移层，漂移层上的主体层，具有与第一导电类型相反的第二导电类型的主体层，以及主体层上的源极区域，源极区域具有第一导电类型导电类型。该器件还包括延伸穿过源极区域和主体层并进入漂移层的沟槽，沟槽的内侧壁上的沟道层，沟道层具有第二导电类型，并且具有与内侧壁相对的内侧壁沟槽，沟道层的内侧壁上的栅极绝缘体和栅极绝缘体上的栅极接触。

34. 发明授权

US08975133B2 Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors 有权
标题翻译：集成电路产品中位于器件级的电容器和制造这种电容器的方法
公开(公告)号：US08975133B2
公开(公告)日：2015-03-10
申请号：US13568802
申请日：2012-08-07
申请人： Kok Yong Yiang , Patrick R. Justison
发明人： Kok Yong Yiang , Patrick R. Justison
IPC分类号： H01L21/8242
CPC分类号： H01L27/0629 , H01L27/0805 , H01L28/60 , H01L29/66181 , H01L29/94
摘要： One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
摘要翻译：本文公开的一种说明性的集成电路产品包括位于半导体衬底上方的金属-1金属化层，位于衬底的表面和金属-1金属化层的底部之间的电容器，其中电容器包括多个导电板，在相对于基板的表面基本正常的方向上定向，以及定位在多个导电板之间的绝缘材料的至少一个区域。

35. 发明授权

US08963223B2 Scalable integrated MIM capacitor using gate metal 有权
标题翻译：使用栅极金属的可扩展集成MIM电容器
公开(公告)号：US08963223B2
公开(公告)日：2015-02-24
申请号：US12660619
申请日：2010-03-01
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L29/94 , H01L27/108 , H01L21/8242 , H01L21/336 , H01L49/02 , H01L23/522 , H01L27/06 , H01L27/08
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L27/0811 , H01L27/092 , H01L28/60 , H01L28/65 , H01L29/4232 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.
摘要翻译：根据一个实施例，半导体管芯中的可扩展集成MIM电容器包括衬底上的高k电介质段和高k电介质段上的金属段，其中金属段形成集成MIM电容器的电容器端子。电容器还包括横向分离连续的电容器端子的填料，其中填料可以用作集成MIM电容器的电容器电介质。在一个实施例中，金属段包括栅极金属。在另一个实施例中，集成MIM电容器基本上与一个或多个晶体管同时形成，而不需要额外的制造工艺步骤。

36. 发明授权

US08941210B2 Semiconductor devices having a trench isolation layer and methods of fabricating the same 有权
标题翻译：具有沟槽隔离层的半导体器件及其制造方法
公开(公告)号：US08941210B2
公开(公告)日：2015-01-27
申请号：US14445291
申请日：2014-07-29
申请人： SK Hynix Inc.
发明人： Tai Ho Kim
IPC分类号： H01L21/70 , H01L29/04 , H01L21/8242 , H01L21/76 , H01L29/06
CPC分类号： H01L29/0649 , H01L21/70 , H01L21/76229 , H01L29/04
摘要： Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.
摘要翻译：提供包括沟槽隔离层的半导体器件。所述半导体器件包括其中具有沟槽的衬底，覆盖所述沟槽的底表面和侧壁的衬垫绝缘层，并且包括位于所述衬垫绝缘层的底部内角处的微沟槽，填充所述微沟槽的第一隔离绝缘层和由所述衬垫绝缘层包围的所述沟槽的下部区域，以及填充所述第一隔离绝缘层上的所述沟槽的第二隔离绝缘层。在沟槽的上部区域的侧壁上的衬垫绝缘层具有朝向沟槽的底表面逐渐增加的厚度，并且沟槽下部区域的侧壁上的衬垫绝缘层具有均匀的厚度。还提供了相关方法。

37. 发明授权

US08916435B2 Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory 有权
标题翻译：用于金属高K绝缘子金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US08916435B2
公开(公告)日：2014-12-23
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/8242 , H01L27/12 , H01L27/108 , H01L49/02 , H01L21/84 , H01L29/94
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

38. 发明授权

US08906763B2 Method of manufacturing a dynamic random access memory (DRAM) including forming contact pads of adjacent cells by laterally etching a contact opening of a cell therebetween 有权
标题翻译：制造动态随机存取存储器（DRAM）的方法，包括通过横向蚀刻其间的单元的接触开口来形成相邻单元的接触垫
公开(公告)号：US08906763B2
公开(公告)日：2014-12-09
申请号：US13540816
申请日：2012-07-03
申请人： Jong-Chul Park , Byung-Jin Kang , Sang-Sup Jeong
发明人： Jong-Chul Park , Byung-Jin Kang , Sang-Sup Jeong
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/768
CPC分类号： H01L27/10888 , H01L21/76816 , H01L21/76897 , H01L27/10855 , H01L27/10876 , H01L27/10894
摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.
摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。封盖绝缘层填充掩模图案的部分之间的间隙。第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

39. 发明授权

US08895322B2 Method for making semiconductor device having ferroelectric capacitor therein 有权
标题翻译：用于制造其中具有铁电电容器的半导体器件的方法
公开(公告)号：US08895322B2
公开(公告)日：2014-11-25
申请号：US13271527
申请日：2011-10-12
申请人： Hideaki Kikuchi , Kouichi Nagai
发明人： Hideaki Kikuchi , Kouichi Nagai
IPC分类号： H01L21/00 , H01L21/8242 , H01L21/31 , H01L27/115 , H01L21/768 , H01L49/02
CPC分类号： H01L27/11507 , H01L21/76834 , H01L27/11502 , H01L28/57 , H01L28/65
摘要： A ferroelectric capacitor provided with a ferroelectric film (10a) is formed above a semiconductor substrate, and thereafter a wiring (17) directly connected to electrodes (9a, 11a) of a ferroelectric capacitor is formed. Then, a silicon oxide film (18) covering the wiring (17) is formed. As the silicon oxide film (18), a film which has processability higher than that of an aluminum oxide film is formed. Besides, a degree of damage that occurs in the ferroelectric capacitor when the insulating film is formed is equal to or less than that when an aluminum oxide film is formed.
摘要翻译：在半导体衬底上形成设置有铁电体膜（10a）的强电介质电容器，然后形成与铁电电容器的电极（9a，11a）直接连接的配线（17）。然后，形成覆盖布线（17）的氧化硅膜（18）。作为氧化硅膜（18），形成具有比氧化铝膜高的加工性的膜。此外，当形成绝缘膜时在铁电电容器中发生的一定程度的损伤等于或小于形成氧化铝膜时的损伤程度。

40. 发明授权

US08890214B2 Method of manufacturing sidewall spacers on a memory device 有权
公开(公告)号：US08890214B2
公开(公告)日：2014-11-18
申请号：US13335578
申请日：2011-12-22
申请人： Panda Durga , Jaydip Guha , Robert Kerr
发明人： Panda Durga , Jaydip Guha , Robert Kerr
IPC分类号： H01L31/0328 , H01L21/8242 , H01L27/105 , H01L29/66
CPC分类号： H01L29/6656 , H01L21/02164 , H01L21/0217 , H01L21/31111 , H01L21/823431 , H01L27/105 , H01L27/1052 , H01L27/10844 , H01L27/10873 , H01L27/10894 , H01L29/6653
摘要： The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

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