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41. 发明申请

US20110185116A1 Memory device with vertically embedded non-flash non-volatile memory for emulation of NAND flash memory 有权
公开(公告)号：US20110185116A1
公开(公告)日：2011-07-28
申请号：US13065823
申请日：2011-03-29
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C5/02 , G11C13/0002 , G11C16/102 , G11C16/16 , G11C2213/71 , Y02D10/13
摘要： A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.

42. 发明申请

US20110163780A1 Field programmable gate arrays using resistivity-sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US20110163780A1
公开(公告)日：2011-07-07
申请号：US12932902
申请日：2011-03-08
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

43. 发明申请

US20110151617A1 Memory and methods of forming the same to enhance scalability of non-volatile two-terminal memory cells 审中-公开
标题翻译：存储器和形成方法，以增强非易失性两端存储单元的可扩展性
公开(公告)号：US20110151617A1
公开(公告)日：2011-06-23
申请号：US12653895
申请日：2009-12-18
申请人： Julie Casperson Brewer
发明人： Julie Casperson Brewer
IPC分类号： H01L21/16
CPC分类号： H01L27/101 , G11C13/0007 , G11C2013/0073 , G11C2213/71
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to scale memory elements, such as implemented in BEOL third dimensional memory technology, independent of operational characteristics. In at least some embodiments, a method to fabricate a non-volatile two-terminal memory device includes depositing a first electrode at a first temperature in a first region in relation to a substrate (e.g., a silicon wafer) that includes active circuitry that was previously fabricated FEOL on the substrate, fabricating a memory element coupled to the first electrode, and optionally, forming at least a portion of a non-ohmic device electrically coupled with the memory element. Further, the method can include depositing a second electrode at a second temperature in a second region in relation to the substrate. In some embodiments, the second temperature is approximately equal to or greater than the first temperature.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和用于缩放存储元件的方法，诸如在BEOL第三维存储器技术中实现的，与操作特性无关。在至少一些实施例中，制造非易失性双端存储器件的方法包括相对于衬底（例如，硅晶片）在第一区域中的第一温度下沉积第一电极，该衬底包括有源电路在衬底上预先制造的FEOL，制造耦合到第一电极的存储元件，以及可选地形成与存储元件电耦合的非欧姆器件的至少一部分。此外，该方法可以包括在相对于衬底的第二区域中在第二温度下沉积第二电极。在一些实施例中，第二温度近似等于或大于第一温度。

44. 发明申请

US20110149636A1 Ion barrier cap 失效
标题翻译：离子屏障盖
公开(公告)号：US20110149636A1
公开(公告)日：2011-06-23
申请号：US12803810
申请日：2010-07-06
申请人： Lawrence Schloss , Rene Meyer , Wayne Kinney , Roy Lamberston , Julie Casperson Brewer
发明人： Lawrence Schloss , Rene Meyer , Wayne Kinney , Roy Lamberston , Julie Casperson Brewer
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.
摘要翻译：由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。与电绝缘层接触的导电氧化物层是可移动离子的源。编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

45. 发明申请

US20110149634A1 Non-volatile memory device ion barrier 失效
标题翻译：非易失性存储器件离子屏障
公开(公告)号：US20110149634A1
公开(公告)日：2011-06-23
申请号：US12653838
申请日：2009-12-18
申请人： Lawrence Schloss , Rene Meyer , Wayne Kinney , Roy Lambertson , Julie Casperson Brewer
发明人： Lawrence Schloss , Rene Meyer , Wayne Kinney , Roy Lambertson , Julie Casperson Brewer
IPC分类号： G11C11/00 , H01L45/00 , H01L29/12
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.
摘要翻译：由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。与电绝缘层接触的导电氧化物层是可移动离子的源。编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

46. 发明授权

US07961529B1 Processor including vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers 有权
标题翻译：处理器包括垂直堆叠的第三维嵌入式可重写非易失性存储器和寄存器
公开(公告)号：US07961529B1
公开(公告)日：2011-06-14
申请号：US12927795
申请日：2010-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C5/04 , G11C7/062 , G11C13/004 , G11C13/02 , G11C2013/0054 , G11C2013/009 , G11C2207/063 , G11C2213/13 , G11C2213/71
摘要： A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
摘要翻译：非易失性寄存器包括存储元件。存储元件包括第一端和第二端。非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。寄存器逻辑位于存储器元件下方。存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。通过在两个端子上施加预定幅度和/或极性的写入电压，可以将新数据写入到两端存储元件。两端存储器元件在没有电源的情况下保留存储的数据。可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。

47. 发明授权

US07961527B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
公开(公告)号：US07961527B2
公开(公告)日：2011-06-14
申请号：US12657385
申请日：2010-01-19
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

48. 发明申请

US20110133147A1 Continuous plane of thin-film materials for a two-terminal cross-point memory 审中-公开
标题翻译：用于两端交叉点存储器的薄膜材料的连续平面
公开(公告)号：US20110133147A1
公开(公告)日：2011-06-09
申请号：US12931773
申请日：2011-02-09
申请人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jon Bornstein , David Hansen
发明人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jon Bornstein , David Hansen
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165 , Y10S257/903
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译：公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。包层导体可以包括由铜制成的芯材料。

49. 发明申请

US20110062989A1 State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories 失效
标题翻译：使用非易失性可重写两端电阻率敏感存储器的状态机
公开(公告)号：US20110062989A1
公开(公告)日：2011-03-17
申请号：US12927546
申请日：2010-11-15
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/173
CPC分类号： G05B19/045 , G05B2219/23289 , G11C13/00
摘要： State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array.
摘要翻译：公开了使用电阻率敏感记忆元件的状态机。状态机包括下一状态逻辑，其包括包括电阻率敏感存储元件和接收输入的非易失性存储器，连接到下一状态逻辑的状态存储设备，该状态存储器包括连接以将状态机的状态提供给下一个状态状态逻辑，输出连接到状态寄存器以输出状态机的状态。电阻率敏感存储元件可以是两端电阻率敏感存储元件。两端电阻率敏感存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性读取的多个导电率分布，并且可以通过施加写入电压来写入新的数据终端。两端电阻率敏感存储器元件在没有电力的情况下保存存储的数据，并且可以被配置为两端交叉点存储器阵列。

50. 发明授权

US07903485B2 Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory 有权
标题翻译：用于补偿一个或多个垂直堆叠非易失性嵌入式存储器层中的有缺陷的非易失性嵌入式存储器的集成电路和方法
公开(公告)号：US07903485B2
公开(公告)日：2011-03-08
申请号：US12807836
申请日：2010-09-14
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C29/00
CPC分类号： G11C5/02 , G11C29/808
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地涉及用于补偿第三维存储器技术中的有缺陷的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为补偿有缺陷的存储器单元。例如，集成电路可以包括具有设置在多层存储器中的存储器单元的存储器。它还可以包括配置为将存储器单元的子集替换为一个或多个有缺陷的存储器单元的存储器回收电路。存储器单元的子集中的至少一个存储单元驻留在存储器中的不同于所述一个或多个缺陷存储器单元中的至少一个的不同平面中。

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