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    • 2. 发明授权
    • Molecular memory device
    • 分子记忆装置
    • US07157750B2
    • 2007-01-02
    • US10899873
    • 2004-07-27
    • Vladimer BulovicAaron MandellAndrew Perlman
    • Vladimer BulovicAaron MandellAndrew Perlman
    • H01L31/00
    • G11C13/0009B82Y10/00G11C13/0014G11C2213/13G11C2213/77Y10S977/943
    • A novel memory cell is provided with an active region including a molecular system and ionic complexes distributed in the molecular system. A pair of write electrodes are arranged for writing information to the memory cell. The active region is responsive to an electric field applied between the pair of write electrodes for switching between an on state and an off state. The active region has a high impedance in the off state and a low impedance in the on state. A pair of read electrodes is used to detect whether the active region is in the on state or in the off state to read the information from the memory cell. Read electrodes may be made of different materials having different work functions to reduce leakage current.
    • 提供了一种新颖的记忆单元,其具有包括分子系统中分子系统和分子系统分布的离子络合物的活性区域。 布置一对写入电极用于将信息写入存储单元。 有源区域响应于在一对写入电极之间施加的电场,用于在导通状态和断开状态之间切换。 有源区在断开状态下具有高阻抗,在导通状态下具有低阻抗。 一对读取电极用于检测有源区域是处于导通状态还是处于断开状态以从存储单元读取信息。 读取电极可以由具有不同功函数的不同材料制成,以减少漏电流。
    • 6. 发明申请
    • Non-volatile register
    • 非易失性寄存器
    • US20090196087A1
    • 2009-08-06
    • US12012641
    • 2008-02-05
    • Robert Norman
    • Robert Norman
    • G11C11/21G11C7/00
    • G11C13/0069G11C5/04G11C7/062G11C13/004G11C13/02G11C2013/0054G11C2013/009G11C2207/063G11C2213/13G11C2213/71
    • A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
    • 公开了一种非易失性寄存器。 非易失性寄存器包括存储元件。 存储元件包括第一端和第二端。 非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。 寄存器逻辑位于存储器元件下方。 存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。 通过在两个端子上施加预定幅度和/或极性的写入电压,可以将新数据写入到两端存储元件。 两端存储器元件在没有电源的情况下保留存储的数据。 可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。
    • 8. 发明申请
    • Non-volatile register
    • 非易失性寄存器
    • US20100238713A1
    • 2010-09-23
    • US12800289
    • 2010-05-11
    • Robert Norman
    • Robert Norman
    • G11C11/00G11C7/06
    • G11C13/0069G11C5/04G11C7/062G11C13/004G11C13/02G11C2013/0054G11C2013/009G11C2207/063G11C2213/13G11C2213/71
    • A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
    • 公开了一种非易失性寄存器。 非易失性寄存器包括存储元件。 存储元件包括第一端和第二端。 非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。 寄存器逻辑位于存储器元件下方。 存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。 通过在两个端子上施加预定幅度和/或极性的写入电压,可以将新数据写入到两端存储元件。 两端存储器元件在没有电源的情况下保留存储的数据。 可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。