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41. 发明授权

US6064216A Apparatus for testing semiconductor wafers 有权
标题翻译：半导体晶片测试装置
公开(公告)号：US6064216A
公开(公告)日：2000-05-16
申请号：US241553
申请日：1999-02-01
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
摘要翻译：提供了一种用于测试半导体晶片的方法，装置和系统。该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

42. 发明授权

US6060339A Method and apparatus providing redundancy for fabricating highly reliable memory modules 失效
标题翻译：提供用于制造高度可靠的存储器模块的冗余的方法和装置
公开(公告)号：US6060339A
公开(公告)日：2000-05-09
申请号：US902470
申请日：1997-07-29
申请人： Salman Akram , James M. Wark , David R. Hembree
发明人： Salman Akram , James M. Wark , David R. Hembree
IPC分类号： H01L23/538 , H05K1/00 , H05K3/22 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/5382 , H01L24/97 , H05K1/0292 , H05K1/0295 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/14 , H05K2201/0979 , H05K2201/10159 , H05K2201/10674
摘要： A method and apparatus for repair of a multi-chip module such as a memory module is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.
摘要翻译：提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中至少一个冗余或辅助芯片连接位置设置在多芯片模块的基板上。辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

43. 发明授权

US06048750A Method for aligning and connecting semiconductor components to substrates 失效
公开(公告)号：US06048750A
公开(公告)日：2000-04-11
申请号：US977312
申请日：1997-11-24
申请人： David R. Hembree
发明人： David R. Hembree
IPC分类号： H01L21/68 , H01L21/44
CPC分类号： H01L21/681
摘要： A method and apparatus for aligning and connecting objects, such as semiconductor components and substrates, are provided. The apparatus includes a hexapod with a moving platform for holding an object for movement in six degrees of freedom. The apparatus also includes a chuck assembly for holding a mating object in a stationary position. A camera and a height gauge are mounted on the moving platform to allow determination of the position and orientation of the object on the chuck assembly. Likewise, a camera and a height gauge are mounted on the chuck assembly to allow determination of the position and orientation of the object on the moving platform. The hexapod includes linear actuators operable by a controller upon signal input from the cameras and height gauges. The apparatus can be used to electrically connect semiconductor dice and chip scale packages to interconnects for testing. In addition, the apparatus can be used for bonding dice to substrates and leadframes, for probe testing semiconductor wafers, and for aligning and connecting spaced components, such as a baseplate and display screen of a field emission display.

44. 发明授权

US6033548A Rotating system and method for electrodepositing materials on semiconductor wafers 失效
标题翻译：用于在半导体晶片上电沉积材料的旋转系统和方法
公开(公告)号：US6033548A
公开(公告)日：2000-03-07
申请号：US901921
申请日：1997-07-28
申请人： Salman Akram , David R. Hembree
发明人： Salman Akram , David R. Hembree
IPC分类号： C25D7/12 , C25F7/00 , H01L21/288 , C25D17/00 , C25F3/00
CPC分类号： C25D7/12 , C25D17/001 , C25F7/00 , H01L21/2885
摘要： An electrochemical reaction assembly and methods of inducing electrochemical reactions, such as for deposition of materials on semiconductor substrates. The assembly and method achieve a highly uniform thickness and composition of deposition material or uniform etching or polishing on the semiconductor substrates by retaining the semiconductor substrates on a cathode immersed in an appropriate reaction solution wherein a wire mesh anode rotates about the continuous moving cathode during electrochemical reaction.
摘要翻译：电化学反应组件和诱导电化学反应的方法，例如用于在半导体衬底上沉积材料。组装和方法通过将半导体衬底保持在浸入合适的反应溶液中的阴极上实现沉积材料的高度均匀的厚度和组成或在半导体衬底上的均匀蚀刻或抛光，其中线网阳极在电化学期间围绕连续移动的阴极旋转反应。

45. 发明授权

US6025728A Semiconductor package with wire bond protective member 失效
标题翻译：半导体封装带引线键合保护元件
公开(公告)号：US6025728A
公开(公告)日：2000-02-15
申请号：US845782
申请日：1997-04-25
申请人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
发明人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01079 , H01L2924/16195
摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.
摘要翻译：提供了一种用于测试半导体晶片的封装，系统和方法。该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

46. 发明授权

US5955877A Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US5955877A
公开(公告)日：1999-09-21
申请号：US170844
申请日：1998-10-13
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H05K13/08 , G01R31/311 , H01L2924/12042 , H01L2924/14 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

47. 发明授权

US5915977A System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
标题翻译：用于与凸起的半导体部件进行临时电连接的系统和互连
公开(公告)号：US5915977A
公开(公告)日：1999-06-29
申请号：US138612
申请日：1998-08-24
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

48. 发明授权

US5893726A Semiconductor package with pre-fabricated cover and method of fabrication 失效
标题翻译：具有预制盖的半导体封装和制造方法
公开(公告)号：US5893726A
公开(公告)日：1999-04-13
申请号：US990866
申请日：1997-12-15
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

49. 发明授权

US5726075A Method for fabricating microbump interconnect for bare semiconductor dice 失效
标题翻译：用于制造裸半导体晶片的微型块互连的方法
公开(公告)号：US5726075A
公开(公告)日：1998-03-10
申请号：US624991
申请日：1996-03-29
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
IPC分类号： H01L21/48 , H01L21/60 , H01L21/28
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042
摘要： A method for forming an interconnect for a bare semiconductor is provided. The interconnect includes an insulating film with a pattern of conductors and microbumps adapted to make an electrical connection with contact locations on the die. The insulating film and conductors are mounted to a rigid substrate (e.g., silicon) using an lo elastomeric adhesive. The method includes forming conductive bus bars in electrical communication with the pattern of conductors to provide an electrical path for electroplating the microbumps onto the conductors. Following the electroplating step, the bus bars are severed and separate electrical paths are formed to the conductors. The bus bar can also be used in the completed interconnect to provide a common electrical path to select conductors. The interconnect can be used for testing the die or for providing a permanent electrical connection to the die.
摘要翻译：提供了一种用于形成裸半导体的互连的方法。互连包括绝缘膜，其具有适于与裸片上的接触位置进行电连接的导体和微胶片图案。绝缘膜和导体使用弹性体粘合剂安装到刚性基底（例如硅）上。该方法包括形成与导体图案电连通的导电母线，以提供用于将微胶片电镀到导体上的电路径。在电镀步骤之后，母线被切断，并且与导体形成分开的电路径。母线也可用于完成的互连，以提供选择导体的公共电路。互连可用于测试管芯或提供与管芯的永久电连接。

50. 发明授权

US5541525A Carrier for testing an unpackaged semiconductor die 失效
标题翻译：用于测试未封装半导体芯片的载体
公开(公告)号：US5541525A
公开(公告)日：1996-07-30
申请号：US345064
申请日：1994-11-14
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/75 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/16145 , H01L2224/48 , H01L2224/75 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution mechanism for biasing the die and interconnect together. The interconnect includes a substrate having raised contact members adapted to penetrate bond pads, or tests pads, on the die to form an electrical connection. Conductive traces are formed on the substrate in electrical communication with the raised contact members and connect to external connectors formed on the base. The interconnect is adapted for testing a particular type of die but is interchangeable with other interconnects to permit testing of different types of dice using a universal carrier.
摘要翻译：提供了用于测试未封装的半导体管芯的载体。承运人包括：基地; 用于建立管芯和外部测试电路之间的电通信的临时互连; 用于将互连件固定到基座的保持机构; 以及用于偏压模具并互连在一起的力分配机构。互连包括具有凸起的接触构件的衬底，该衬底适于穿过模具上的接合焊盘或测试衬垫以形成电连接。导电迹线形成在与凸起接触构件电连通的基板上，并连接到形成在基座上的外部连接器。互连适用于测试特定类型的管芯，但可与其他互连互换，以允许使用通用载体测试不同类型的管芯。

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