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1. 发明授权

US08704380B2 Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods 有权
标题翻译：使用这种方法形成的微特征器件和微特征器件的晶片级封装方法
公开(公告)号：US08704380B2
公开(公告)日：2014-04-22
申请号：US12874644
申请日：2010-09-02
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28 , H01L23/02 , H01L21/00
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/73259 , H01L2224/81005 , H01L2225/06513 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/18161
摘要： Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.
摘要翻译：本文公开了使用这种方法形成的微特征装置和微特征装置的晶片级封装的方法。根据本发明的实施例的用于封装微特征器件的方法可以包括以期望的布置将多个第一已知的良好微电子管芯可释放地附接到载体衬底。在几个实施例中，例如，第一模具可以可释放地附接到载体基底上的附着特征。该方法还可以包括将一个或多个第二已知的良好的微电子管芯以堆叠的结构附接到各个第一管芯以形成多个堆叠的器件。该方法还包括至少部分地封装堆叠的装置并将堆叠的装置彼此分离。

2. 发明授权

US08546931B2 Stacked semiconductor components having conductive interconnects 有权
标题翻译：具有导电互连的堆叠半导体部件
公开(公告)号：US08546931B2
公开(公告)日：2013-10-01
申请号：US13076505
申请日：2011-03-31
申请人： Alan G. Wood , William M. Hiatt , David R. Hembree
发明人： Alan G. Wood , William M. Hiatt , David R. Hembree
IPC分类号： H01L23/02 , H01L23/52
CPC分类号： H01L21/76898 , H01L21/4885 , H01L21/6835 , H01L21/6836 , H01L23/3114 , H01L23/481 , H01L23/4951 , H01L23/4985 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/50 , H01L24/78 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/86 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06102 , H01L2224/06136 , H01L2224/11003 , H01L2224/1131 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/2518 , H01L2224/45015 , H01L2224/451 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/4824 , H01L2224/4845 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/78301 , H01L2224/8121 , H01L2224/81815 , H01L2224/85001 , H01L2224/851 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/19042 , Y10T29/53187 , Y10T29/53209 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2224/83851 , H01L2224/05552
摘要： A stacked semiconductor component includes a semiconductor substrate having a substrate contact, a substrate opening extending to an inner surface of the substrate contact, and a conductive interconnect comprising a wire in the substrate opening having a wire bonded connection with the inner surface of the substrate contact. The stacked semiconductor component also includes a second substrate stacked on the semiconductor substrate having a contact bonded to the conductive interconnect on the semiconductor substrate. The second substrate can also include conductive interconnects in the form of wire bonded wires, and the stacked semiconductor substrate can include a third semiconductor substrate stacked on the second substrate.
摘要翻译：堆叠半导体部件包括具有基板接触的半导体基板，延伸到基板接触件的内表面的基板开口以及包括在基板开口中的线的导电布线，该导线具有与基板接触件的内表面的引线接合连接。堆叠的半导体部件还包括堆叠在半导体衬底上的第二衬底，其具有接合到半导体衬底上的导电互连的接触。第二基板还可以包括导线接合线形式的导电互连，并且堆叠的半导体衬底可以包括堆叠在第二衬底上的第三半导体衬底。

3. 发明授权

US08513797B2 Stacked semiconductor component having through wire interconnect (TWI) with compressed wire 有权
标题翻译：具有通过电线互连（TWI）与压缩线的堆叠的半导体部件
公开(公告)号：US08513797B2
公开(公告)日：2013-08-20
申请号：US13480528
申请日：2012-05-25
申请人： Alan G. Wood , David R. Hembree
发明人： Alan G. Wood , David R. Hembree
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate.
摘要翻译：半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。通线互连（TWI）包括穿过基板接触件和基板的通孔，通孔中的压接线接合到基板触点，以及在导线上的接触。堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。

4. 发明授权

US08502353B2 Through-wafer interconnects for photoimager and memory wafers 失效
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US08502353B2
公开(公告)日：2013-08-06
申请号：US13154550
申请日：2011-06-07
申请人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

5. 发明授权

US08404523B2 Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI) 有权
标题翻译：用于封装通过导线互连（TWI）制造堆叠半导体系统的方法
公开(公告)号：US08404523B2
公开(公告)日：2013-03-26
申请号：US13534038
申请日：2012-06-27
申请人： David R. Hembree , Alan G. Wood
发明人： David R. Hembree , Alan G. Wood
IPC分类号： H01L23/04
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.
摘要翻译：一种制造具有封装的通过导线互连的层叠半导体系统的方法包括提供具有第一侧，第二侧和基板接触的基板; 在基板接触中形成通孔，将基板形成到第二面; 将电线放在通孔中; 在靠近第一侧的导线上形成第一触点，并且在靠近第二侧的导线上形成第二触点; 并在第一侧上形成聚合物层，留下暴露的第一接触。该方法还包括堆叠两个或更多个基板并且电连接基板上的通孔互连线。

6. 发明授权

US08324100B2 Methods of forming conductive vias 有权
标题翻译：形成导电通孔的方法
公开(公告)号：US08324100B2
公开(公告)日：2012-12-04
申请号：US13029950
申请日：2011-02-17
申请人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.
摘要翻译：形成导电通孔的方法可以包括部分地穿过衬底形成盲孔，在衬底的表面上形成铝膜，从一些表面去除铝膜的第一部分，将导电材料选择性地沉积到第二部分上铝膜，并且通过基板的背面露出盲孔。制造导电通孔的方法可以包括通过至少一个未镀覆的焊盘形成至少一个通孔，在至少一个通孔的至少一个表面上形成第一粘合剂，在第一粘合剂上形成电介质，形成基底层叠在电介质和至少一个未镀覆的焊盘上，并将镍镀在基底层上。

7. 发明授权

US08294273B2 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US08294273B2
公开(公告)日：2012-10-23
申请号：US12985570
申请日：2011-01-06
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

8. 发明授权

US08120167B2 System with semiconductor components having encapsulated through wire interconnects (TWI) 有权
标题翻译：具有通过线互连（TWI）封装的半导体部件的系统
公开(公告)号：US08120167B2
公开(公告)日：2012-02-21
申请号：US12904314
申请日：2010-10-14
申请人： David R. Hembree , Alan G. Wood
发明人： David R. Hembree , Alan G. Wood
IPC分类号： H01L23/00
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
摘要翻译：一种用封装的直通线互连制造半导体部件的方法包括以下步骤：提供具有第一面，第二面和基板接触的基板; 在基板接触中形成通孔，将基板形成到第二面; 将电线放置在通孔中; 在靠近第一侧的导线上形成第一触点，并且在靠近第二侧的导线上形成第二触点; 并在第一侧上形成聚合物层，留下暴露的第一接触。聚合物层可以使用薄膜辅助成型方法形成，包括以下步骤：在粘合部件的顶端部分上形成模具膜，模制聚合物层，然后移除模具膜以暴露粘合部件的末端部分。通线互连提供了在半导体衬底的相对侧上具有触点的多电平互连。

9. 发明申请

US20110089539A1 PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS 有权
标题翻译：包装微电子图像和包装微电子图像的方法
公开(公告)号：US20110089539A1
公开(公告)日：2011-04-21
申请号：US12977686
申请日：2010-12-23
申请人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
发明人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
IPC分类号： H01L23/544 , H01L23/48
CPC分类号： H01L27/146 , H01L21/76898 , H01L27/14618 , H01L27/148 , H01L31/02016 , H01L2224/48227 , H01L2924/01046 , H01L2924/01066 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front side with integrated circuit interconnects thereon. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.
摘要翻译：本文公开了在微电子器件和微电子器件中形成导电晶片间互连的方法。在一个实施例中，微电子器件可以包括具有集成电路的单片微电子衬底，其前侧具有集成电路互连。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连延伸穿过衬底并与接合焊盘接触。互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

10. 发明申请

US20110074043A1 METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES 有权
标题翻译：在半导体衬底和结构结构中形成VIAS的方法
公开(公告)号：US20110074043A1
公开(公告)日：2011-03-31
申请号：US12955359
申请日：2010-11-29
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L23/48
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，可以通过从活性表面通过其上的导电元件和导电元件下面的基底的一部分形成部分通孔来形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

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