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41. 发明授权

US5315130A Very high density wafer scale device architecture 失效
标题翻译：非常高密度的晶圆秤设备架构
公开(公告)号：US5315130A
公开(公告)日：1994-05-24
申请号：US502256
申请日：1990-03-30
申请人： James W. Hively , Mammen Thomas , Richard L. Bechtel
发明人： James W. Hively , Mammen Thomas , Richard L. Bechtel
IPC分类号： G11C5/02 , G11C11/406 , G11C29/00 , G11C29/28 , H01L27/02
CPC分类号： G11C29/28 , G11C11/406 , G11C5/025 , H01L27/0207
摘要： This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure. The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing for good and bad elements. The structure may include two or more address ports, which may simultaneously address different banks of the repeating elements, which feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology.
摘要翻译：本发明涉及晶片尺寸集成电路的设计和制造。晶片尺寸集成电路的较低层包括电隔离的重复块，例如电路元件的逻辑元件或块。上导电层包括数据和地址总线结构。可以对位于上层和下层之间的任意通孔层进行图案化。通孔层的图案化避免了将总线结构连接到有缺陷的元件或块，建立元件的地址，并建立了寻址结构和数据结构的组织。通孔图案被图案化以在测试好和坏元素之后将上总线线路连接到较低金属层中的选定区域。该结构可以包括两个或更多个地址端口，其可以同时寻址重复元件的不同组，该特征对于动态随机存取存储器（DRAM）的自动刷新和/或用于与其他存储器类型的多个寻址特别有用。该架构提供了在定制通孔级别时确定的晶圆级规器件的最终功能组织中的灵活性。开销控制电路的总体减少和重复块的减小的尺寸提供了比使用相同水平的制造技术的常规单芯片集成电路可实现的每个晶片更高的总密度。

42. 发明授权

US5223741A Package for an integrated circuit structure 失效
标题翻译：集成电路结构的封装
公开(公告)号：US5223741A
公开(公告)日：1993-06-29
申请号：US402202
申请日：1989-09-01
申请人： Richard L. Bechtel , Mammen Thomas , James W. Hively
发明人： Richard L. Bechtel , Mammen Thomas , James W. Hively
IPC分类号： H01L23/057 , H01L23/373 , H01L25/16
CPC分类号： H01L23/057 , H01L23/3736 , H01L25/16 , H01L2224/45014 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/16152 , H01L2924/19107 , H01L2924/3025
摘要： A package for housing a large scale semiconductor integrated circuit structure, such as a wafer or an assemblage of chips in a hybrid configuration, comprises a heat spreading and dissipating base plate to which the wafer or hybrid circuit is directly bonded. Electrical connections from the periphery of the package interior to the wafer are preferably made with equal length TAB (Tape Automated Bonding) strips connected to electrically conductive pads located along a diameter of the wafer or the centerline of the hybrid circuit. If hermeticity is desired, the integrated circuit structure is encircled by a boundary strip of sandwich construction through which signals are routed, and to which a lid is attached. For hermeticity, the integrated circuit structure is surrounded on all sides with a barrier combining metal and ceramic; the remainder of the package may be constructed from conventional printed circuit board materials. The package can be made arbitrarily large without encountering the problems typically associated with hermetic structures which utilize large areas of ceramic materials.
摘要翻译：用于容纳大规模半导体集成电路结构的封装，例如晶片或混合配置的芯片组合，包括直接结合晶片或混合电路的散热和散热底板。优选地，从封装内部到晶片的周边的电连接制成具有相等长度的TAB（带自动接合）带，其连接到沿着晶片的直径或混合电路的中心线定位的导电焊盘。如果需要气密性，集成电路结构被三明治结构的边界条包围，通过该夹层结构的边界条通过信号被路由并且附接有盖。为了气密性，集成电路结构在所有方面被包围金属和陶瓷的屏障; 封装的其余部分可以由常规印刷电路板材料构成。该包装可以任意大，而不会遇到通常与利用大面积陶瓷材料的密封结构相关的问题。

43. 发明授权

US4929992A MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions 失效
标题翻译： MOS晶体管结构，具有与栅极，源极和漏极区域的自对准硅化物接触
公开(公告)号：US4929992A
公开(公告)日：1990-05-29
申请号：US869759
申请日：1986-06-02
申请人： Mammen Thomas , Matthew Weinberg
发明人： Mammen Thomas , Matthew Weinberg
IPC分类号： H01L21/768 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/76819 , H01L21/8249 , Y10S257/90
摘要： An improved integrated circuit structure is disclosed comprising MOS devices formed with at least raised polysilicon gate contact portions. Metal silicide is formed over at least a portion of the source and drain regions to provide conductive paths to the source and drain contacts. In a preferred embodiment, the source and drain contacts also comprise raised contacts which are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sufficiently to expose the upper surface of all of the contacts.
摘要翻译：公开了一种改进的集成电路结构，其包括形成有至少凸起的多晶硅栅极接触部分的MOS器件。金属硅化物形成在源极和漏极区域的至少一部分上，以提供到源极和漏极触点的导电路径。在优选实施例中，源触点和漏极触点也包括隆起的触点，其也由相同的多晶硅层形成，以允许形成具有自对准触点的高度平坦化的结构，该自对准触点通过平坦化形成在结构上的绝缘层而充分暴露于所有触点的上表面。

44. 发明授权

US4789760A Via in a planarized dielectric and process for producing same 失效
标题翻译：通过平面化电介质及其制造方法
公开(公告)号：US4789760A
公开(公告)日：1988-12-06
申请号：US728962
申请日：1985-04-30
申请人： Linda J. Koyama , Mammen Thomas , Harry J. Levinson
发明人： Linda J. Koyama , Mammen Thomas , Harry J. Levinson
IPC分类号： H01L21/3205 , H01L21/311 , H01L21/768 , H05K1/00
CPC分类号： H01L21/76804 , H01L21/31111 , H01L21/76877
摘要： An improved integrated circuit structure is disclosed wherein a first metal layer is coated with a dielectric material and another metal layer is applied over the dielectric layer and a via electrically interconnects at least a portion of the first metal layer with at least a portion of the second metal layer. The via is formed having a lower first width dimension adjacent the first metal layer and an upper enlarged width portion adjacent the second metal layer formed by masking the dielectric with a mask having an opening conforming to the first dimension and isotropically etching the dielectric through the mask to provide the enlarged portion adjacent the upper surface of the dielectric.
摘要翻译：公开了一种改进的集成电路结构，其中第一金属层被电介质材料涂覆，并且另一金属层被施加在电介质层上，并且通孔使第一金属层的至少一部分与第二金属层的至少一部分电互连金属层。通孔形成为具有与第一金属层相邻的较低的第一宽度尺寸和邻近第二金属层的上部扩大宽度部分，该第二金属层通过用具有与第一尺寸相符的开口的掩模掩蔽电介质而形成，并且通过掩模各向异性蚀刻电介质以提供邻近电介质的上表面的扩大部分。

45. 发明授权

US4688314A Method of making a planar MOS device in polysilicon 失效
标题翻译：在多晶硅中制作平面MOS器件的方法
公开(公告)号：US4688314A
公开(公告)日：1987-08-25
申请号：US782842
申请日：1985-10-02
申请人： Matthew Weinberg , Mammen Thomas
发明人： Matthew Weinberg , Mammen Thomas
IPC分类号： H01L21/285 , H01L21/60 , H01L21/8234 , H01L29/08 , H01L21/76 , H01L21/225
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/8234 , H01L29/0847
摘要： A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with at least one portion defined therein for formation of a source/gate/drain region for an MOS device. All of the contacts of the device are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.
摘要翻译：描述具有至少一个MOS器件的高度平坦化的集成电路结构以及制造该结构的方法。该结构包括其上生长有场氧化物的衬底，其中限定有至少一个部分，用于形成用于MOS器件的源极/栅极/漏极区域。器件的所有触点都是使用填充场氧化物中限定部分的多晶硅形成的，形成高度平坦化的结构。

46. 发明授权

US4672420A Integrated circuit structure having conductive, protective layer for multilayer metallization to permit reworking 失效
标题翻译：集成电路结构，具有用于多层金属化的导电保护层，以允许返工
公开(公告)号：US4672420A
公开(公告)日：1987-06-09
申请号：US722957
申请日：1985-04-12
申请人： Yan Borodovsky , Mammen Thomas , Danny Ma
发明人： Yan Borodovsky , Mammen Thomas , Danny Ma
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/525 , H01L23/532 , H01L23/14 , H01L23/54
CPC分类号： H01L21/76897 , H01L23/525 , H01L23/53223 , H01L23/53271 , H01L2924/0002
摘要： An improved integrated circuit structure, and method of making the structure, is disclosed wherein at least one metallization layer is coated during production of the structure with a conductive layer capable of withstanding metal removal means, and an upper metallization layer is subsequently applied to the structure. At least a portion of the subsequent metallization layer is in ohmic contact with the conductive layer and the lower metallization layer is protected by the intervening conductive layer during subsequent removal of the upper metallization layer if subsequent reworking of the structure becomes necessary. In a preferred embodiment, the use of the conductive layer over a metallization layer further enhances the construction process during patterning of a photoresist applied over the conductive layer by the use of a conductive material having antireflective properties.
摘要翻译：公开了一种改进的集成电路结构和制造该结构的方法，其中在具有能够承受金属去除装置的导电层的结构生产期间至少涂覆一个金属化层，随后将上部金属化层施加到该结构。后续金属化层的至少一部分与导电层欧姆接触，并且如果随后的结构的再加工变得必要，则随后去除上部金属化层期间，下部金属化层被中间导电层保护。在优选实施例中，在金属化层上使用导电层进一步增强了通过使用具有抗反射特性的导电材料在施加在导电层上的光致抗蚀剂图案化期间的构造过程。

47. 发明授权

US4669179A Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions 失效
标题翻译：用于形成具有外部基极区域的双极晶体管的集成电路制造工艺
公开(公告)号：US4669179A
公开(公告)日：1987-06-02
申请号：US794357
申请日：1985-11-01
申请人： Matthew Weinberg , Mammen Thomas , Shiao-Hoo Chang
发明人： Matthew Weinberg , Mammen Thomas , Shiao-Hoo Chang
IPC分类号： H01L21/8222 , H01L21/265 , H01L21/331 , H01L21/762 , H01L27/06 , H01L29/10 , H01L29/73 , H01L21/203 , H01L27/02
CPC分类号： H01L21/2652 , H01L21/762 , H01L29/1004 , Y10S148/01
摘要： An integrated circuit bipolar transistor fabrication technique is disclosed. The process includes steps to form shallow, self-aligned, heavily doped, extrinsic base regions which do not encroach substantially upon the emitter region. The process allows for construction of transistors which require a thinner epitaxial layer or, in the alternative, i.e., with a typical epitaxial layer, have a higher collector-to-base breakdown voltage.
摘要翻译：公开了集成电路双极晶体管制造技术。该方法包括形成浅的，自对准的，重掺杂的非本征碱基区域的步骤，其不会基本上侵蚀发射极区域。该工艺允许构建需要更薄外延层的晶体管，或者在替代方案中，即具有典型的外延层，具有较高的集电极到基极击穿电压。

48. 发明授权

US4654824A Emitter coupled logic bipolar memory cell 失效
公开(公告)号：US4654824A
公开(公告)日：1987-03-31
申请号：US683078
申请日：1984-12-18
申请人： Mammen Thomas , Wen C. Ko
发明人： Mammen Thomas , Wen C. Ko
IPC分类号： G11C11/411 , H01L21/74 , H01L21/8222 , H01L27/102 , G11C11/40 , G11C11/36
CPC分类号： H01L21/74 , G11C11/4116 , H01L21/8222 , H01L27/1025
摘要： An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

49. 发明申请

US20220071825A1 Patient Puller 有权
公开(公告)号：US20220071825A1
公开(公告)日：2022-03-10
申请号：US17017577
申请日：2020-09-10
申请人： Mammen Thomas , Sarah Peter , Elizabeth Thomas
发明人： Mammen Thomas , Sarah Peter , Elizabeth Thomas
IPC分类号： A61G7/10
摘要： A pulling mechanism using a motor, and a rolling tube or rod of sufficient strength to pull a patient lying on a sheet on the bed is provided to move patients up the bed with little manual effort. In most hospitals and care facilities a common problem is that patients tend to slip down the beds causing discomfort for the patient. Patients have to be moved-up to comfortable position on the bed. Currently this is done manually by two nursing staff one on either side of the bed, with the patient on a slide sheet and pulling the patient manually up using the slide sheet. This simple but strenuous operation has been the cause of back problems for many nursing staff. The current invention is a way to reduce or eliminate this injury to nursing staff by mechanizing the pull-up operation.

50. 发明授权

US09519608B2 PCI express to PCI express based low latency interconnect scheme for clustering systems 有权
标题翻译： PCI Express基于PCI Express的低延迟互联方案用于集群系统
公开(公告)号：US09519608B2
公开(公告)日：2016-12-13
申请号：US14588937
申请日：2015-01-03
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H04N13/04 , G06F13/40 , H04L12/931 , G06F13/42
CPC分类号： G06F13/4282 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , H04L49/40
摘要： PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
摘要翻译： PCI Express是一种总线或I / O互连标准，用于计算机或嵌入式系统内部，可实现更快的数据传输到外围设备。该标准仍在不断发展，但已经达到了一定程度的稳定性，使其他应用程序可以使用PCIE作为基础来实现。一种基于PCIE的互连方案，可实现多个支持PCIE的系统之间的交换和互连，每个PCIE系统都具有自己的PCIE根系，因此PCIE架构的可扩展性可以应用于连接系统之间的数据传输以形成系统集群。提出。这些连接的系统可以是任何计算，控制，存储或嵌入式系统。互连的可扩展性将允许集群在系统变得必要时增加带宽，而不改变到不同的连接体系结构。

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