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41. 发明授权

US07795936B2 Data center tracking circuit and semiconductor integrated circuit including the same 有权
标题翻译：数据中心跟踪电路和半导体集成电路包括相同
公开(公告)号：US07795936B2
公开(公告)日：2010-09-14
申请号：US12174579
申请日：2008-07-16
申请人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/093 , H04L7/033
摘要： A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.
摘要翻译：数据中心跟踪电路包括时钟树，感测块和延迟补偿块。时钟树包括串联连接的多个时钟缓冲器，缓冲时钟，并输出输出信号。感测块基于时钟感测输出信号的相位变化，并输出感测信号。延迟补偿块响应于感测信号调整提供给时钟树的电流，并调整输出信号的相位。

42. 发明授权

US07733727B2 Receiver circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储器的接收电路
公开(公告)号：US07733727B2
公开(公告)日：2010-06-08
申请号：US12172108
申请日：2008-07-11
申请人： Tae-Jin Hwang , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C11/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
摘要翻译：本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间到第一和第二偏移信号。

43. 发明授权

US07667493B2 Data transmitter 失效
标题翻译：数据发送器
公开(公告)号：US07667493B2
公开(公告)日：2010-02-23
申请号：US12164948
申请日：2008-06-30
申请人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
发明人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
IPC分类号： H03K19/0175
CPC分类号： G11C7/1051 , G11C7/1057 , H04L25/4902 , H04L25/4917
摘要： Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.
摘要翻译：数据发射机包括终止于第一电平的第一和第二输出节点，被配置为产生通过在低功率模式期间逻辑地组合第一和第二数据而被激活的关闭信号的控制器，配置成驱动第一或第二电平的第一驱动器输出节点响应于第一数据到第二级，第二驱动器被配置为响应于第二数据以与第一驱动器不同的驱动力将第一或第二输出节点驱动到第二级，第二驱动器当关闭信号被激活时被关闭。

44. 发明申请

US20090302965A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090302965A1
公开(公告)日：2009-12-10
申请号：US12266787
申请日：2008-11-07
申请人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： H01P9/00
CPC分类号： H04B3/32 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K2005/00071 , H04L25/0272 , H04L25/0286 , H04L25/029
摘要： A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.
摘要翻译：半导体器件包括用于传送信号的传输线和转换检测器，每个传输线检查多条传输线中的每条传输线上的传输信号是否被转换。如果信号被转移，则检测其转换形状。信号模式确定单元响应于来自多个转换检测器的输出信号来确定相邻传输线之间的信号传输模式。延迟单元耦合到各个传输线，用于根据来自信号模式确定单元的相应输出信号来调整传输信号的传输延迟。

45. 发明申请

US20090128200A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090128200A1
公开(公告)日：2009-05-21
申请号：US12175224
申请日：2008-07-17
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
摘要翻译：能够控制建立/保持时间的接收机电路包括：第一相位发送单元，被配置为通过在与第一时钟信号同步的同时根据多个检测电平检测输入数据来生成第一输出信号，以及控制第一输入信号的建立/保持时间基于第一偏移电压的电平的输出信号，被配置为根据第一代码来控制第一输出信号的电压电平的电平转换器;以及第二相位发送单元，被配置为接收电平转换器的输出信号作为第二偏移电压，同时与第二时钟信号同步，通过根据检测电平检测输入数据产生第二输出信号，并控制第二输出信号的建立/保持时间。

46. 发明授权

US07990785B2 Delay locked loop circuit of semiconductor device 有权
标题翻译：半导体器件的延迟锁定环路
公开(公告)号：US07990785B2
公开(公告)日：2011-08-02
申请号：US12262517
申请日：2008-10-31
申请人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , H03L7/0812 , H03L7/089 , H03L7/095
摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
摘要翻译：半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

47. 发明授权

US07868663B2 Receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的接收器电路
公开(公告)号：US07868663B2
公开(公告)日：2011-01-11
申请号：US12171214
申请日：2008-07-10
申请人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Ic-Su Oh , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H04L7/0337
摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
摘要翻译：一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度电压来控制读出放大器的驱动速度。

48. 发明授权

US07808841B2 Data output circuit for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据输出电路
公开(公告)号：US07808841B2
公开(公告)日：2010-10-05
申请号：US12169568
申请日：2008-07-08
申请人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
发明人： Hae-Rang Choi , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
IPC分类号： G11C7/10 , G11C7/06 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/028 , G11C29/1201 , G11C29/50
摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.
摘要翻译：一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器，其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。输出节点上的电压电平是输出信号的电压电平。

49. 发明授权

US07633318B2 Data receiver of semiconductor integrated circuit and method for controlling the same 失效
标题翻译：半导体集成电路的数据接收器及其控制方法
公开(公告)号：US07633318B2
公开(公告)日：2009-12-15
申请号：US12176215
申请日：2008-07-18
申请人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G01R19/00 , H03H7/30
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.
摘要翻译：半导体集成电路的数据接收器包括：放大器，其通过根据反馈数据使用均衡功能检测和放大接收数据来输出放大信号;检测单元，其检测在放大器中未接收到数据的周期，并输出检测信号以及均衡功能控制单元，其响应于检测信号停止放大器的均衡功能。

50. 发明申请

US20090273995A1 APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：用于在半导体存储器件中移除晶体管的装置
公开(公告)号：US20090273995A1
公开(公告)日：2009-11-05
申请号：US12347518
申请日：2008-12-31
申请人： Ji-Wang LEE , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang LEE , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/02 , G11C5/063 , G11C7/1078 , G11C7/1084
摘要： An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines.
摘要翻译：一种用于去除半导体存储器件中的串扰的装置包括用于接收外部提供的信号的焊盘，用于将由每个焊盘接收的信号传递到设备中的相应元件的传输线以及耦合在相邻线之间的电容器，以便调整信号的传输延迟取决于相邻线路之间的信号传输模式。

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