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41. 发明授权

US07250347B2 Double-gate FETs (Field Effect Transistors) 失效
标题翻译：双栅极FET（场效应晶体管）
公开(公告)号：US07250347B2
公开(公告)日：2007-07-31
申请号：US10905979
申请日：2005-01-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/78648 , H01L29/78654
摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.
摘要翻译：一种用于形成具有相互对准的双栅极的晶体管的方法。该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

42. 发明授权

US07233071B2 Low-k dielectric layer based upon carbon nanostructures 有权
标题翻译：基于碳纳米结构的低k电介质层
公开(公告)号：US07233071B2
公开(公告)日：2007-06-19
申请号：US10711764
申请日：2004-10-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L23/48
CPC分类号： H01L21/02115 , B82Y10/00 , H01L21/02282 , H01L21/3146 , H01L21/3185 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76831 , H01L21/76888 , H01L2221/1047
摘要： A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.
摘要翻译：用于制造半导体器件的低k电介质材料，使用低k电介质材料的半导体结构，以及形成这种介电材料和制造这种结构的方法。低k介电材料包括碳纳米结构，如碳纳米管或碳棒球，其特征在于绝缘电子状态。碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。将碳纳米结构转化为绝缘电子态的一种方法是氟化。

43. 发明授权

US07229889B2 Methods for metal plating of gate conductors and semiconductors formed thereby 有权
标题翻译：由此形成的栅极导体和半导体的金属电镀方法
公开(公告)号：US07229889B2
公开(公告)日：2007-06-12
申请号：US10906881
申请日：2005-03-10
申请人： Steven J. Holmes , Charles W. Koburger, III , David V. Horak , Toshiharu Furukawa , Mark C. Hakey
发明人： Steven J. Holmes , Charles W. Koburger, III , David V. Horak , Toshiharu Furukawa , Mark C. Hakey
IPC分类号： H01L21/20
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795
摘要： A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.
摘要翻译：提供了一种对半导体上的栅极导体进行金属镀覆的方法。该方法包括在半导体上限定有机聚合物电镀心轴，激活有机聚合物电镀心轴的一个或多个位点，以及将种子层结合到一个或多个活化位点。然后可以将金属导电材料电镀在种子层上以形成栅极导体。还提供了其上镀有宽度在约1至约7纳米之间的栅极导体的半导体器件。

44. 发明授权

US06891226B2 Dual gate logic device 失效
标题翻译：双门逻辑器件
公开(公告)号：US06891226B2
公开(公告)日：2005-05-10
申请号：US10448729
申请日：2003-05-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
IPC分类号： H01L21/76 , H01L21/02 , H01L21/28 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66484 , H01L21/2807 , H01L29/7831 , H01L29/78645 , H01L29/78648
摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.
摘要翻译：本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。采用单晶硅晶片作为通道材料。自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。

45. 发明授权

US06759315B1 Method for selective trimming of gate structures and apparatus formed thereby 失效
标题翻译：选择性修整栅极结构的方法及由此形成的装置
公开(公告)号：US06759315B1
公开(公告)日：2004-07-06
申请号：US09224759
申请日：1999-01-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/76888 , H01L21/76895
摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.
摘要翻译：在晶体管中形成修整栅极的方法包括以下步骤：在半导体衬底上形成多晶硅栅极导体，并通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法来修整多晶硅部分。修整步骤可以选择性地补偿n沟道和p沟道器件。此外，修整膜可以任选地通过从各向异性和各向同性蚀刻中选择的方法去除。此外，可以通过生长膜的各向异性蚀刻形成栅极导体间隔物。所得到的晶体管可以包括栅极导体的经修剪的多晶硅部分，其中通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法进行修整。

46. 发明授权

US06506653B1 Method using disposable and permanent films for diffusion and implant doping 失效
标题翻译：使用一次性和永久性膜进行扩散和注入掺杂的方法
公开(公告)号：US06506653B1
公开(公告)日：2003-01-14
申请号：US09524677
申请日：2000-03-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.
摘要翻译：提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。沉积保形层并用掺杂剂注入。执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

47. 发明授权

US06387783B1 Methods of T-gate fabrication using a hybrid resist 失效
标题翻译：使用混合抗蚀剂的T型栅极制造方法
公开(公告)号：US06387783B1
公开(公告)日：2002-05-14
申请号：US09299267
申请日：1999-04-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L2128
CPC分类号： H01L29/42316 , H01L21/28581
摘要： Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.
摘要翻译：提供了在衬底上形成T形栅的方法，其采用混合抗蚀剂。采用混合抗蚀剂专门用于以非常高的分辨率在衬底上限定T形栅极的基极。为了限定T栅极的基极，在衬底上沉积混合抗蚀剂层。提供了具有边缘的掩模版特征的掩模，并且位于混合抗蚀剂层之上，使得掩模版特征的边缘高于用于T形栅极的基底的期望位置。此后，混合抗蚀剂层通过掩模暴露于辐射，并且暴露的混合抗蚀剂层被显影以在T形栅极的底部限定开口。优选地，在曝光期间通过掩模版特征在混合抗蚀剂层中形成的环形特征被修整。 T栅极可以通过采用任何已知的T栅极制造技术来完成。

48. 发明授权

US06333533B1 Trench storage DRAM cell with vertical three-sided transfer device 失效
标题翻译：沟槽存储DRAM单元，具有垂直三面传输设备
公开(公告)号：US06333533B1
公开(公告)日：2001-12-25
申请号：US09394964
申请日：1999-09-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.
摘要翻译：一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

49. 发明授权

US06333245B1 Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer 失效
标题翻译：使用锗氧化物牺牲层将掺杂剂引入半导体器件的方法
公开(公告)号：US06333245B1
公开(公告)日：2001-12-25
申请号：US09469137
申请日：1999-12-21
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Donald W. Rakowski
IPC分类号： H01L2122
CPC分类号： H01L29/66575 , H01L21/2255 , H01L21/823814 , H01L21/823842
摘要： A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.
摘要翻译：公开了一种使用掺杂的氧化锗将掺杂剂引入半导体器件的方法。该方法包括使用快速热退火（RTA）或炉退火来从半导体衬底上的掺杂的锗氧化物牺牲层将掺杂剂扩散到衬底中。退火之后将掺杂剂扩散到衬底中，使用水去除锗氧化物牺牲层，从而避免在栅极或标准器件隔离结构中去除二氧化硅（SiO 2），这可能导致器件故障。 N +和p +源极和漏极可以在半导体衬底中的适当的阱中使用单一退火形成，并且不需要限定第一掺杂牺牲层的不止一个区域。或者，在将第二掺杂剂引入到氧化锗牺牲层中之前的退火给出较慢的扩散离子，例如砷开始。

50. 发明授权

US06303272B1 Process for self-alignment of sub-critical contacts to wiring 失效
标题翻译：亚临界触点自动对准布线的过程
公开(公告)号：US06303272B1
公开(公告)日：2001-10-16
申请号：US09192140
申请日：1998-11-13
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03C500
CPC分类号： H01L21/76811 , H01L21/76813 , H01L21/76897 , H01L24/45 , H01L24/85 , H01L2224/451 , H01L2224/85 , H01L2924/00014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patterned first on the upper layer. The wiring pattern trenches are etched through the thinner surface layer, and partially through the second, thicker layer. After the wiring pattern is etched, the contacts for the wiring layer are printed as line/space patterns which intersect the wiring pattern. The contact pattern is etched into the lower, thicker layer with an etch process that is selective to the upper thinner layer. The contact is only formed at the intersection point of the wiring image with the contact image, therefore the contact is self-aligned to the metal.
摘要翻译：一种用于在与集成电路的布线图形自对准的集成电路上形成触点的方法。在该方法中，在衬底上形成较厚的第一材料的下层和较薄的第二材料的上层。金属布线的特征首先在上层形成。通过更薄的表面层蚀刻布线图案沟槽，并部分地穿过第二较厚的层。在布线图案被蚀刻之后，布线层的触点被印刷为与布线图案相交的线/间隔图形。通过对上部较薄层选择性的蚀刻工艺将接触图案蚀刻到下部更厚的层中。接触仅在接线图像与接触图像的交点处形成，因此触点与金属自对准。

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