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41. 发明申请

US20120105050A1 METHOD AND SYSTEM FOR VARYING SAMPLING FREQUENCY TO AVOID SOFTWARE HARMONICS WHEN SAMPLING DIGITAL POWER INDICATORS 有权
标题翻译：在采样数字功率指示器时，改变采样频率以避免软件谐波的方法和系统
公开(公告)号：US20120105050A1
公开(公告)日：2012-05-03
申请号：US12917947
申请日：2010-11-02
申请人： Samuel D. Naffziger , Suresh B. Periyacheri
发明人： Samuel D. Naffziger , Suresh B. Periyacheri
IPC分类号： G01R19/00
CPC分类号： G01R31/31721 , G06F1/3203 , G06F1/3206 , G06F1/3234 , Y02D10/00 , Y02D10/10
摘要： A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC.
摘要翻译：本文描述了在采样数字功率指示器时改变采样频率以避免软件谐波的方法和系统。功率监视器可以基于可变延迟时间的可变采样率重复采样IC器件的多个信号以获得能量值。可变延迟时间可以基于伪随机值或可预测值。可变延迟时间可以指示可以插入在能量值的重复样本之间的延迟周期的数量。能量值样本之间可变数量的延迟周期可能产生可变采样率。可变采样率可能避免与软件谐波的对准，这可能导致功耗不准确的表示。通过对IC的该部分的能量值进行重复取样而获得的多个样本可以相加以产生IC的该部分的累积能量值。

42. 发明申请

US20120023345A1 MANAGING CURRENT AND POWER IN A COMPUTING SYSTEM 有权
标题翻译：管理计算系统中的电流和功率
公开(公告)号：US20120023345A1
公开(公告)日：2012-01-26
申请号：US12840813
申请日：2010-07-21
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3243 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.
摘要翻译：一种用于模具上有效功率传输的系统和方法。半导体芯片在裸片上包括利用至少两个不同的电压调节器和功率管理器的两个或多个计算单元（CU）。电源管理器在检测到给定CU的活动电平低于给定阈值时，通过芯片重新分配功率信息。响应于接收到相应数量的捐赠功率信用，所述一个或多个所选择的CU中的每一个保持具有高性能P状态的高活动级别。当相应的工作量增加时，每个CU通过在至少两个不同的操作电压之间交替来维持对应于高性能P状态的操作和平均功耗。当交变期间工作电压下降时，由特定CU吸引的电流可能会超过给定的电流限制。电源管理器检测到超出此电流限制，从而重新分配芯片上的功率信息。

43. 发明授权

US07661003B2 Systems and methods for maintaining performance of an integrated circuit within a working power limit 失效
标题翻译：用于在工作功率极限内保持集成电路性能的系统和方法
公开(公告)号：US07661003B2
公开(公告)日：2010-02-09
申请号：US11040394
申请日：2005-01-21
申请人： Samuel D. Naffziger , Christopher A. Poirier
发明人： Samuel D. Naffziger , Christopher A. Poirier
IPC分类号： G06F1/32 , G06F1/26 , G01R31/00
CPC分类号： G06F1/3203 , G06F1/28
摘要： Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.
摘要翻译：公开了用于维持集成电路性能的系统和方法。系统的一个实施例可以包括工作功率限制评估器，其确定作为与影响集成电路的性能的变化相关联的至少一个性能因素的函数的工作功率极限。该系统还可以包括功率管理系统，其基于工作功率极限和集成电路的实际功率来改变集成电路的功率以维持基本上恒定的性能。

44. 发明申请

US20090256593A1 PROGRAMMABLE SAMPLE CLOCK FOR EMPIRICAL SETUP TIME SELECTION 有权
标题翻译：用于实际设置时间选择的可编程时钟
公开(公告)号：US20090256593A1
公开(公告)日：2009-10-15
申请号：US12100052
申请日：2008-04-09
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H03K19/096
CPC分类号： H03K3/35625 , H03K3/0375
摘要： A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon.
摘要翻译：一种用于有效改进更快处理器设计的时序分析的系统和方法，对芯片面积的影响可以忽略不计。不是为半导体芯片上的触发器电路提供单个时钟，而是使用分离时钟。触发器接收主锁存器的主时钟信号，并为从锁存器接收单独的从时钟信号。主和从时钟门控电路耦合到全局时钟分配系统和本地触发器。主时钟门电路接收用于选择延迟的延迟控制信号，其中所选择的延迟确定主时钟信号在从时钟信号转变之后转变的附加时间量。在半导体芯片上使用延迟的主时钟可以允许定时路径具有更多的计算时间而不增加时钟周期时间。此外，可以选择延迟来固定后硅中的定时路径。

45. 发明授权

US07533285B2 Synchronizing link delay measurement over serial links 有权
标题翻译：通过串行链路同步链路延迟测量
公开(公告)号：US07533285B2
公开(公告)日：2009-05-12
申请号：US10830375
申请日：2004-04-22
申请人： Samuel D. Naffziger , Eric M. Rentschler
发明人： Samuel D. Naffziger , Eric M. Rentschler
IPC分类号： G06F1/04 , H04L7/00
CPC分类号： H04J3/0682 , H04L7/0033
摘要： Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.
摘要翻译：提供了与同步链路延迟相关联的系统，方法和其他实施例。在一个示例性系统中，用于使第一电子部件与由一个或多个串行通信链路连接的第二电子部件之间的信号通信同步的系统包括偏移逻辑，该偏移逻辑被配置为将所选择的偏移应用于信号传输，以引起第一以及将信号传输的两个方向同步的第二电子部件。同步逻辑被配置为确定第一和第二电子部件之间的信号传输的单向延迟，并且被配置为控制偏移逻辑以应用所选择的偏移。

46. 发明授权

US07157895B2 Systems and methods for generating a current 有权
标题翻译：用于生成电流的系统和方法
公开(公告)号：US07157895B2
公开(公告)日：2007-01-02
申请号：US10700919
申请日：2003-11-04
申请人： Samuel D. Naffziger , William P. Repasky , Christopher Jonathan Bostak
发明人： Samuel D. Naffziger , William P. Repasky , Christopher Jonathan Bostak
IPC分类号： G05F3/16
CPC分类号： G05F3/242 , G05F3/262 , H03M1/745
摘要： Systems and methods are provided for generating a current. A first current source generates a first current based on a first current selection signal, and a second current source generates a second current that is a multiple of the first current in response to selection of the first current.
摘要翻译：提供了用于产生电流的系统和方法。第一电流源基于第一电流选择信号产生第一电流，并且响应于第一电流的选择，第二电流源产生作为第一电流的倍数的第二电流。

47. 发明授权

US06954706B2 Method for measuring integrated circuit processor power demand and associated system 有权
标题翻译：集成电路处理器电力需求和相关系统的测量方法
公开(公告)号：US06954706B2
公开(公告)日：2005-10-11
申请号：US10644376
申请日：2003-08-20
申请人： Christopher A. Poirier , Samuel D. Naffziger , Christopher J. Bostak
发明人： Christopher A. Poirier , Samuel D. Naffziger , Christopher J. Bostak
IPC分类号： G01R19/00 , G01R21/133 , G01R31/28 , G01R31/317 , G01R35/00 , G06F19/00 , H01L23/34
CPC分类号： G01R31/31721 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.
摘要翻译：一种用于测量集成电路处理器功率需求的系统和方法包括校准一个或多个压控振荡器，用作电流表，校准校准电流源，其中校准电流源通过固有电阻来吸取电流，校准固有电阻，并交织所述使用在固有电阻上测量的电压计算处理器功率需求时，可以及时校准。

48. 发明授权

US06943586B2 Method and system to temporarily modify an output waveform 有权
公开(公告)号：US06943586B2
公开(公告)日：2005-09-13
申请号：US10646935
申请日：2003-08-22
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G01R31/30 , G01R31/28 , G01R31/317 , G06F1/04 , H03K5/06 , H03K19/0185 , H03K19/003
CPC分类号： G06F1/04 , G01R31/31725 , H03K5/06 , H03K19/018585
摘要： Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to the associated circuit. The clock waveform is modified to include an intermediate level between the normally high and low levels over a cycle in a second operating mode.

49. 发明授权

US06697929B1 Scannable zero-catcher and one-catcher circuits for reduced clock loading and power dissipation 失效
标题翻译：可扫描的零捕获和捕捉电路，可减少时钟负载和功耗
公开(公告)号：US06697929B1
公开(公告)日：2004-02-24
申请号：US09504004
申请日：2000-02-14
申请人： Brian S. Cherkauer , Samuel D. Naffziger
发明人： Brian S. Cherkauer , Samuel D. Naffziger
IPC分类号： G06F132
CPC分类号： G06F11/25 , G01R31/318533 , G01R31/318572
摘要： A method and apparatus for scannable zero-catcher and one-catcher circuits. The catcher circuit of the present invention comprises an input stage. A feedback stage is coupled to the input stage. Scanning logic is coupled to the feedback stage. An output stage is coupled to the feedback stage.
摘要翻译：一种用于可扫描零捕获器和捕捉器电路的方法和装置。本发明的捕获电路包括输入级。反馈级耦合到输入级。扫描逻辑耦合到反馈级。输出级耦合到反馈级。

50. 发明授权

US06643828B2 Method for controlling critical circuits in the design of integrated circuits 有权
标题翻译：集成电路设计中关键电路的控制方法
公开(公告)号：US06643828B2
公开(公告)日：2003-11-04
申请号：US10016861
申请日：2001-12-14
申请人： Samuel D. Naffziger , Wayne D. Kever
发明人： Samuel D. Naffziger , Wayne D. Kever
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068
摘要： A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.
摘要翻译：在电路库中提供关键电路的方法，由此这些关键电路允许设计者以受控的方式对它们进行修改，使得变化易于实现并且几乎保证是正确的。本发明包括一种对这些关键电路进行有限修改以以受控方式改变其特性的方法，然后用电路模拟器检查所得到的修改电路，以便符合已经为该库关键电路组装的预定规范。

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