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41. 发明授权

US07870527B2 Method for stacked pattern design of printed circuit board and system thereof 有权
标题翻译：印刷电路板的堆叠图案设计方法及其系统
公开(公告)号：US07870527B2
公开(公告)日：2011-01-11
申请号：US11970744
申请日：2008-01-08
申请人： Ming-Chin Tsai
发明人： Ming-Chin Tsai
IPC分类号： G06F17/50
CPC分类号： G06N3/126 , G06F17/5068 , H05K3/0005 , H05K3/4611 , H05K2201/0352 , H05K2201/09736
摘要： A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked pattern is inputted into operational interface of the software; Next, initial solution sets of stacked pattern are generated; Then, duplications of the initial solution sets of stacked pattern are generated according to a fitness function; Afterward, crossover of the duplications of stacked pattern are performed at random; Then, mutations are executed by a probability at random; Finally, identification is performed to check if the solution approaches the standard of demand and the result of stacked pattern is shown; otherwise, operational step jumps to duplicate step and repeats above steps until satisfying solution is obtained. The most suitable way for package can be arranged out through making especially mathematical calculations by the system efficiently.
摘要翻译：公开了一种利用遗传算法设计PCB堆叠图案的方法及其系统。该方法包括以下步骤：首先将堆叠模式的信息数据输入软件的操作界面; 接下来，生成堆叠图案的初始解集; 然后，根据适应度函数生成堆叠模式的初始解集的重复; 之后，堆叠图案的重复的交叉随机进行; 然后，以概率随机地执行突变; 最后，进行识别以检查解决方案是否接近需求标准，并显示堆叠模式的结果; 否则，操作步骤跳转到重复步骤，重复上述步骤，直到获得满足的解。最合适的包装方式可以通过系统进行特别的数学计算来排除。

42. 发明申请

US20100237879A1 METHOD AND APPARATUS FOR IMPROVING YIELD RATIO OF TESTING 有权
标题翻译：用于提高测试屈服比的方法和装置
公开(公告)号：US20100237879A1
公开(公告)日：2010-09-23
申请号：US12610270
申请日：2009-10-30
申请人： WEI-PING WANG , Hsuan-Chung KO
发明人： WEI-PING WANG , Hsuan-Chung KO
IPC分类号： G01R27/28
CPC分类号： G01R31/2894 , G01R31/2879
摘要： A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard.
摘要翻译：公开了一种用于提高测试屈服比的方法和装置。该方法包括以下步骤。首先，测试设备并测量电磁干扰。接下来，检查测试结果是否通过测试。然后，如果设备未通过测试，则检查电磁干扰数据是否超过预定标准。如果电磁干扰数据超过预定标准，则再次执行上述步骤。如果设备仍然测试失败并且电磁干扰值仍然超过预定标准，则测试终止。

43. 发明授权

US07772861B2 Probe card 有权
标题翻译：探针卡
公开(公告)号：US07772861B2
公开(公告)日：2010-08-10
申请号：US12259249
申请日：2008-10-27
申请人： Cheng-Chin Ni
发明人： Cheng-Chin Ni
IPC分类号： G01R31/02
CPC分类号： G01R1/07342 , G01R1/06716 , G01R1/06772
摘要： The present invention discloses a probe card for testing a wafer. The probe card comprises a printed circuit board for transmitting test signals, a fastened ring arranged at the downside of the printed circuit board, and a plurality of needles passing through the fastened ring, each needle having one end connecting to circuits of the printed circuit board, and having a tip portion at the other end connecting to a pad of the wafer, where each needle has at least one bent portion between the fastened ring and the tip portion, to absorb stress between the needle and the pad.
摘要翻译：本发明公开了一种用于测试晶片的探针卡。探针卡包括用于传输测试信号的印刷电路板，布置在印刷电路板的下侧的紧固环和穿过紧固环的多根针，每个针的一端连接到印刷电路板的电路并且在另一端具有连接到晶片的焊盘的尖端部分，其中每个针在紧固环和尖端部分之间具有至少一个弯曲部分，以吸收针和衬垫之间的应力。

44. 发明授权

US07701233B2 Heat-resistant lens kit 失效
标题翻译：耐热镜片套件
公开(公告)号：US07701233B2
公开(公告)日：2010-04-20
申请号：US11819083
申请日：2007-06-25
申请人： Tai Pi-Hui
发明人： Tai Pi-Hui
IPC分类号： G01R31/02
CPC分类号： G01R31/2874
摘要： A heat-resistant lens kit configured within the pogo tower of the wafer tester is disclosed. The heat-resistant lens kit has two parallel lenses and a main body with a through hole. The main body and two parallel lenses enclose a vacuum room within the through hole.
摘要翻译：公开了一种配置在晶片测试器的波峰塔内的耐热透镜套件。耐热透镜套件具有两个平行透镜和具有通孔的主体。主体和两个平行透镜在通孔内包围一个真空室。

45. 发明授权

US07501809B2 Electronic component handling and testing apparatus and method for electronic component handling and testing 失效
标题翻译：电子部件处理和电子部件处理和测试的测试装置和方法
公开(公告)号：US07501809B2
公开(公告)日：2009-03-10
申请号：US11652695
申请日：2007-01-12
申请人： Hsieh Chih-Hung
发明人： Hsieh Chih-Hung
IPC分类号： G01R31/28
CPC分类号： G01R31/2893
摘要： The present invention discloses an electronic testing apparatus and a continuous test method for electronic component, which includes multiple test areas, each area possesses respective pick and place module. The apparatus includes multiple shuttles located between the test area and input/output trays. Moreover, a further pick and place module is utilized, between the shuttles and the input/output trays, for picking and placing the devices under test or tested device. The method delivers different electronic component to different test area for testing by different shuttles and to perform testing continuously.
摘要翻译：本发明公开了一种电子元件的电子测试装置和连续测试方法，其包括多个测试区域，每个区域都具有相应的拾放模块。该装置包括位于测试区域和输入/输出托盘之间的多个梭子。此外，在梭子和输入/输出托盘之间，还用于拾取和放置被测器件或被测试器件的另外的拾放模块。该方法将不同的电子元件提供给不同的测试区域，用于通过不同的梭子进行测试，并连续进行测试。

46. 发明公开

US20240153890A1 SEMICONDUCTOR PACKAGE ASSEMBLY AND SEMICONDUCTOR PACKAGE SUBSTRATE MODULE 审中-公开
公开(公告)号：US20240153890A1
公开(公告)日：2024-05-09
申请号：US18193613
申请日：2023-03-30
申请人： King Yuan Electronics Co., Ltd.
发明人： Chia Fong CHOU , Ta Wei CHOU , Hui-Lung HSU
IPC分类号： H01L23/60 , H01L23/00 , H01L23/31
CPC分类号： H01L23/60 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/48137 , H01L2224/49175 , H01L2924/30205
摘要： The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.

47. 发明申请

US20220155361A1 IMAGE TEST SYSTEM, TEST ASSEMBLY AND IMAGE CAPTURE CARD 有权
公开(公告)号：US20220155361A1
公开(公告)日：2022-05-19
申请号：US17472746
申请日：2021-09-13
申请人： King Yuan Electronics Co., Ltd.
发明人： Pin-Yan TSAI , Kuang-Che CHENG
IPC分类号： G01R31/26 , G01R31/308 , G01R31/28
摘要： An image test system includes a test assembly and an image capture card. The test assembly is provided for obtaining a test signal from a test object, and includes an interface conversion circuit for converting signal transmission form of the test signal. The image capture card is provided for obtaining the test signal from the test assembly, and obtaining an image data from the test signal. The image test system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image capture card further includes a pair of clock input pins for obtaining the test signal clock directly from the test object.

48. 发明授权

US09116064B2 Structure of built-in self-test for pressure tester and method thereof 有权
标题翻译：压力测试仪内置自检结构及其方法
公开(公告)号：US09116064B2
公开(公告)日：2015-08-25
申请号：US13728915
申请日：2012-12-27
申请人： King Yuan Electronics Co., LTD
发明人： Wei-Jen Cheng
IPC分类号： G01L27/00
CPC分类号： G01L27/00
摘要： A built-in self-test structure for a pressure tester and a method thereof are provided. The built-in self-test structure includes a substrate, a plurality of membrane layers, a fixing portion, an electrical heating unit and a sensing circuit unit. The membrane layers are formed on the substrate. The fixing portion is configured on the membrane layers and includes a notch. The notch and the membrane layers define a cavity. The electrical heating unit is configured on one membrane layer, and the sensing circuit unit is configured on another membrane layer. The electrical heating unit heats up to increase the pressure in the cavity according to an input voltage, so that the membrane layers have a small deformation. The sensing circuit unit outputs a test signal according to the small deformation.
摘要翻译：提供了一种用于压力测试仪的内置自检结构及其方法。内置的自检结构包括基板，多个膜层，固定部，电加热单元和感测电路单元。膜层形成在基板上。固定部构造在膜层上并且包括凹口。凹口和膜层限定一个空腔。电加热单元配置在一个膜层上，感测电路单元配置在另一个膜层上。电加热单元根据输入电压加热以增加空腔中的压力，使得膜层具有小的变形。感测电路单元根据小的变形输出测试信号。

49. 发明授权

US08751178B2 Method and apparatus for determining disposition of via hole on printed circuit board 有权
标题翻译：用于确定印刷电路板上的通孔的布置的方法和装置
公开(公告)号：US08751178B2
公开(公告)日：2014-06-10
申请号：US13233121
申请日：2011-09-15
申请人： Ming-Chin Tsai
发明人： Ming-Chin Tsai
IPC分类号： G01N37/00
CPC分类号： H05K3/0005 , H05K1/0262 , H05K1/115 , H05K2201/093 , H05K2201/09663
摘要： A method for determining disposition of via hole on printed circuit board (PCB) includes the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on the PCB for intersecting the geometric layout to form a plurality of points of intersection; defining line segments by segmenting the line at each of the points of intersection to form a plurality of line segments; deleting some of the line segments having one end not being point of intersection for the geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in the plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within the smallest closed region.
摘要翻译：一种用于确定印刷电路板（PCB）上的通孔布置的方法包括以下步骤：提供PCB，其上布置有几何布局和通孔; 在PCB上提供与几何布局相交的线以形成多个交点; 通过在每个相交点处分割线来定义线段以形成多个线段; 删除一些线段，其一端不是几何布局的交点，以形成多个分段区域; 通过从所述多个分割区域中的任一点反复搜索区域来搜索封闭区域; 确定封闭区域是否是最小的封闭区域; 确定通孔是否位于最小封闭区域内。

50. 发明申请

US20140083158A1 STRUCTURE OF BUILT-IN SELF-TEST FOR PRESSURE TESTER AND METHOD THEREOF 有权
标题翻译：用于压力测试仪的内置自检结构及其方法
公开(公告)号：US20140083158A1
公开(公告)日：2014-03-27
申请号：US13728915
申请日：2012-12-27
申请人： KING YUAN ELECTRONICS CO., LTD
发明人： Wei-Jen Cheng
IPC分类号： G01L27/00
CPC分类号： G01L27/00
摘要： A built-in self-test structure for a pressure tester and a method thereof are provided. The built-in self-test structure includes a substrate, a plurality of membrane layers, a fixing portion, an electrical heating unit and a sensing circuit unit. The membrane layers are formed on the substrate. The fixing portion is configured on the membrane layers and includes a notch. The notch and the membrane layers define a cavity. The electrical heating unit is configured on one membrane layer, and the sensing circuit unit is configured on another membrane layer. The electrical heating unit heats up to increase the pressure in the cavity according to an input voltage, so that the membrane layers have a small deformation. The sensing circuit unit outputs a test signal according to the small deformation.
摘要翻译：提供了一种用于压力测试仪的内置自检结构及其方法。内置的自检结构包括基板，多个膜层，固定部，电加热单元和感测电路单元。膜层形成在基板上。固定部构造在膜层上并且包括凹口。凹口和膜层限定一个空腔。电加热单元配置在一个膜层上，感测电路单元配置在另一个膜层上。电加热单元根据输入电压加热以增加空腔中的压力，使得膜层具有小的变形。感测电路单元根据小的变形输出测试信号。

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