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41. 发明授权

US09007247B2 Multi-bit sigma-delta modulator with reduced number of bits in feedback path 有权
标题翻译：反馈路径中位数减少的多位Σ-Δ调制器
公开(公告)号：US09007247B2
公开(公告)日：2015-04-14
申请号：US13548069
申请日：2012-07-12
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M3/02 , H03M7/30 , H03M3/00
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.
摘要翻译：用于ADC的Σ-Δ调制器将输入信号传递到环路滤波器，然后传送到调制器的多位量化器。量化器的输出被传递到数字滤波器，并且反馈信号被传回到环路滤波器，反馈信号具有比由多位量化器产生的位少的位。数字滤波器在Σ-Δ调制器的通带中具有大于1的阶数。

42. 发明授权

US08990461B2 On-The-Go (OTG) USB devices configuration method for identifying configuration of other connected devices by reacting to change in resistance value on a resistive line 有权
标题翻译： On-The-Go（OTG）USB设备配置方法，用于通过在电阻线上改变电阻值来识别其他连接设备的配置
公开(公告)号：US08990461B2
公开(公告)日：2015-03-24
申请号：US13392016
申请日：2010-08-25
申请人： Nathalie Ballot , Nicholas Florenchie
发明人： Nathalie Ballot , Nicholas Florenchie
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/426 , Y02D10/14 , Y02D10/151
摘要： The present invention generally relates to the management of a configuration of a first device. The first device includes a control unit and an interface unit managing a communication interface. The communication interface comprises at least one resistive line having a resistance value. The resistance value allows the interface unit to identify a configuration for at least one second device adapted to be linked to the first device via the communication interface. The interface unit: /a/ detects a change of the resistance value on the resistive line corresponding to a configuration of said second device; /b/ processes said change of the resistance value to adapt the configuration of the first device according to the configuration of said second device.
摘要翻译：本发明一般涉及对第一设备的配置的管理。第一设备包括控制单元和管理通信接口的接口单元。通信接口包括具有电阻值的至少一个电阻线。电阻值允许接口单元识别适于经由通信接口链接到第一设备的至少一个第二设备的配置。接口单元：/ a /检测对应于所述第二设备的配置的电阻线上的电阻值的变化; / b /根据所述第二设备的配置处理所述电阻值的改变以适应第一设备的配置。

43. 发明授权

US08958284B2 Port number reservation agent 有权
标题翻译：端口号预约代理
公开(公告)号：US08958284B2
公开(公告)日：2015-02-17
申请号：US13279378
申请日：2011-10-24
申请人： Stefan Runeson
发明人： Stefan Runeson
IPC分类号： H04L29/06 , H04L29/12 , H04W4/00
CPC分类号： H04L69/162 , H04L61/2007 , H04L61/6063 , H04L61/6086 , H04W4/60
摘要： In a communication device having a modem subsystem and an Application Processing Engine (APE) that share an IP address, port number conflicts are avoided by a Port Reservation Agent (PRA) running on the APE. Apps executing on the modem subsystem must request to register a port number with the PRA prior to using it. If the address is available, the PRA creates a port reservation socket and associates the port number with the requesting app. If the requested port number is not available, the PRA returns an error and the app must request a different address. To apps executing on the APE, the port reservation sockets appear as port numbers associated with other apps executing on the APE. In this manner, port number conflicts between the modem subsystem and the APE are avoided.
摘要翻译：在具有共享IP地址的调制解调器子系统和应用处理引擎（APE）的通信设备中，通过在APE上运行的端口预留代理（PRA）来避免端口号冲突。在调制解调器子系统上执行的应用程序必须在PRA使用之前请求注册一个端口号。如果地址可用，则PRA创建一个端口预留套接字，并将端口号与请求应用相关联。如果请求的端口号不可用，则PRA返回错误，并且应用程序必须请求不同的地址。对于在APE上执行的应用程序，端口预留套接字显示为与在APE上执行的其他应用程序相关联的端口号。这样就避免了调制解调器子系统与APE之间的端口号冲突。

44. 发明授权

US08953702B2 Precoding matrix index selection process for a MIMO receiver based on a near-ML detection, and apparatus for doing the same 有权
标题翻译：基于近ML检测的MIMO接收机的预编码矩阵索引选择过程，以及用于进行相同的装置
公开(公告)号：US08953702B2
公开(公告)日：2015-02-10
申请号：US13995766
申请日：2011-12-20
申请人： Sébastien Aubert , Andrea Ancora
发明人： Sébastien Aubert , Andrea Ancora
IPC分类号： H04B7/02 , H04B7/04 , H04B7/06
CPC分类号： H04B7/0456 , H04B7/0452 , H04B7/0639 , H04B7/0697
摘要： A process selects a Precoding Matrix Index (PMI) in a Multiple In Multiple Out (MIMO) receiver used in a wireless communications system including a base station communicating with User Equipments (UE) through a downlink and uplink channel. The base station applies a precoding on the transmit symbol vector based on a matrix selected from a set of predefined matrices and identified by a PMI index computed by the UE and forwarded to the base station via the uplink. The process includes estimating the MIMO channel matrix H of a given set of resources blocks comprising received symbol vectors, estimating the variance σ2 of the additive noise (AWGN), and computing for each particular matrix comprised within the set of predefined matrices a cost function representative of the orthogonality of the matrix MIMO channel matrix H. The process further includes comparing the values of the cost function and transmitting to the base station the index corresponding to the matrix corresponding to the best conditioned MIMO channel matrix according to the comparison of the values.
摘要翻译：一种过程在包括通过下行链路和上行链路信道与用户设备（UE）通信的基站的无线通信系统中使用的多输入多输出（MIMO）接收机中选择预编码矩阵索引（PMI）。基站基于从一组预定义矩阵中选择的矩阵对发射符号向量应用预编码，并由UE计算出的PMI索引识别，并通过上行链路转发给基站。该过程包括估计包括接收到的符号向量的给定资源块集合的MIMO信道矩阵H，估计加性噪声（AWGN）的方差和sgr 2，以及针对包含在该组预定义矩阵内的每个特定矩阵计算成本表示矩阵MIMO信道矩阵H的正交性的函数。该过程进一步包括比较成本函数的值并根据比较的方式比较发送给基站与对应于最佳条件MIMO信道矩阵的矩阵相对应的索引价值观。

45. 发明申请

US20150028825A1 Control Circuit, Control Method, DC-DC Converter and Electronic Device 有权
标题翻译：控制电路，控制方法，DC-DC转换器和电子设备
公开(公告)号：US20150028825A1
公开(公告)日：2015-01-29
申请号：US14378751
申请日：2012-03-07
申请人： ST-Ericsson SA
发明人： Jingwen Mao , Zhiyong Luo , Kaihua Zheng
IPC分类号： H02M3/04 , H02M1/08
CPC分类号： H02M3/04 , H02M1/08 , H02M3/157 , H02M3/1588 , H02M2001/0003 , Y02B70/1466
摘要： A control circuit (115), a control method, a DC-DC converter and an electronic device are provided. The control circuit (115) is used to control the DC-DC converter to switch its operation modes. In the control circuit (115), whether mode of the DC-DC converter is to be switched is judged according to parameters of a first duration of an active duration and a second duration of an inactive duration. Comparison of analogue values is prevented, and as a result, the use of the analogue comparator is reduced, thus the influence of the semiconductor processes on designing a controller can be reduced.
摘要翻译：提供控制电路（115），控制方法，DC-DC转换器和电子设备。控制电路（115）用于控制DC-DC转换器切换其工作模式。在控制电路（115）中，根据活动持续时间的第一持续时间和非活动持续时间的第二持续时间的参数来判断是否要切换DC-DC转换器的模式。可以防止模拟值的比较，结果减少了模拟比较器的使用，从而可以降低半导体工艺对设计控制器的影响。

46. 发明授权

US08913356B2 Composite electronic circuit assembly 有权
标题翻译：复合电子电路组件
公开(公告)号：US08913356B2
公开(公告)日：2014-12-16
申请号：US13266180
申请日：2010-04-20
申请人： Alain Artieri
发明人： Alain Artieri
IPC分类号： H02H9/00 , H01L25/18 , H01L23/50
CPC分类号： H01L23/50 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A composite electronic circuit assembly comprises two MOS or CMOS circuit dice (100, 200) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.
摘要翻译：复合电子电路组件包括叠加在封装内的两个MOS或CMOS电路芯片（100,200）。基于所述模块的数字，模拟或混合特性，电路组件的不同模块分布在两个骰子之间。这种分布使得可以将电路组件的数字模块组合在另一个管芯中的管芯和模拟或混合模块之一中。因此可以减少电路组件的生产成本，开发时间和电能消耗。

47. 发明申请

US20140347128A1 Digital Class-D Amplifier and Digital Signal Processing Method 有权
标题翻译：数字D类放大器和数字信号处理方法
公开(公告)号：US20140347128A1
公开(公告)日：2014-11-27
申请号：US14358182
申请日：2012-10-30
申请人： ST-Ericsson SA
发明人： Carlo Crippa , Rossella Bassoli
IPC分类号： H03F3/185 , H03F3/217 , H03K7/08
CPC分类号： H03F3/185 , H03F3/187 , H03F3/2175 , H03F3/45475 , H03F2200/165 , H03F2200/351 , H03F2200/78 , H03F2203/21112 , H03F2203/21196 , H03K7/08
摘要： A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).
摘要翻译：公开了一种数字D类放大器（10），包括：脉冲宽度调制器（PW Mod），包括：适于接收输入信号（x [n]）和反馈信号（fb [n]）的数字环路滤波器 ]），所述数字环路滤波器（Loop_F）适于以时钟频率（f_s）处理所述输入和反馈信号，以提供经过滤波的数字信号（w [n]）作为输出; PWM转换模块（PW_CM），其具有用于接收经过滤波的数字信号（w [n]）并具有连接到数字环路滤波器（Loop F）的第一输出端25的输入端）用于处理滤波后的数字信号（w [n]）并在所述第一输出端提供反馈信号（fb [n]）。 PWM转换模块（PW_CM）包括：第一比较器（CMP_N），适于将滤波后的数字信号（w [n]）与第一参考三角波形（VTn [n]）进行比较，以提供第一PWM信号 [n]），具有比所述时钟频率（fs）低得多的频率（f_osc）的第一参考三角波形; 适于将滤波后的数字信号（w [n]）与第二参考三角波形（VTp [n]）进行比较以用于提供第二PWM信号（yp [n]）作为输出的第二比较器（CMP_P），第二参考三角形波形（VTp [n]）是第一三角波形（VTn [n]）的倒数，所述第一（yn [n]）和第二（yp [n]）PWM信号表示差分输出脉宽调制信号 [n]，yp [n]）。

48. 发明授权

US08892159B2 Multi-standard transceiver architecture with common balun and mixer 有权
标题翻译：具有普通平衡 - 不平衡转换器和混频器的多标准收发器架构
公开(公告)号：US08892159B2
公开(公告)日：2014-11-18
申请号：US13464070
申请日：2012-05-04
申请人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
发明人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC分类号： H04W88/06 , H04B1/00 , H04B1/04 , H04B1/40
CPC分类号： H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
摘要： A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
摘要翻译：多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。普通的不平衡变压器包括初级线圈和次级线圈。所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或者连接到与第二通信标准相关联的第二放大路径。公共混频器被配置为根据选择了哪个通信标准来向一个信号路径提供上变频信号。

49. 发明授权

US08891698B2 First significant path detection 有权
标题翻译：第一次重要的路径检测
公开(公告)号：US08891698B2
公开(公告)日：2014-11-18
申请号：US12326762
申请日：2008-12-02
申请人： Stefania Sesia , Giuseppe Montalbano , Pierre Demaj
发明人： Stefania Sesia , Giuseppe Montalbano , Pierre Demaj
IPC分类号： H03D1/04 , H04B1/7115 , H04B1/7117
CPC分类号： H04B1/7115 , H04B1/7117
摘要： A scheme determines the first significant path (FSP) of a received multipath signal, from data defining the relative delay and the amplitude of the individual signal paths occurring in a series of time frames. The scheme includes filtering the data to spread the signal paths, performing a persistence test between frames to reject spurious signal paths, combining the energy of the signal paths in a frame, applying a test to determine the time at which the combined energy satisfies a criterion, and selecting the FSP dependent on that time. The combined energy may be evaluated within a sliding window, and the position of the window within the frame determined that maximizes the combined energy. Alternatively, the combined energy may be evaluated as the cumulative energy through the frame, and the position determined at which the cumulative energy reaches a threshold.
摘要翻译：方案从定义在一系列时间帧中出现的各个信号路径的相对延迟和振幅的数据确定接收的多路径信号的第一有效路径（FSP）。该方案包括对数据进行滤波以扩展信号路径，在帧之间执行持续测试以抑制寄生信号路径，组合帧中的信号路径的能量，应用测试来确定组合能量满足标准的时间，并根据该时间选择FSP。可以在滑动窗口内评估组合的能量，并且确定框架内的窗口的位置使得组合能量最大化。或者，可以将组合的能量评估为通过该帧的累积能量，以及确定累积能量达到阈值的位置。

50. 发明授权

US08891495B2 Process for slot synchronization of the P-SCH sequence in a UMTS communication system and a receiver for the same 有权
标题翻译：用于UMTS通信系统中的P-SCH序列的时隙同步的处理和用于其的接收机的处理
公开(公告)号：US08891495B2
公开(公告)日：2014-11-18
申请号：US13512482
申请日：2010-11-29
申请人： Andrea Ancora , Fabrizio Tomatis
发明人： Andrea Ancora , Fabrizio Tomatis
IPC分类号： H04L12/26 , H04B1/7083 , H04B1/7075 , H04W56/00
CPC分类号： H04B1/70755 , H04B1/7083 , H04W56/00
摘要： A Process for achieving slot synchronization of the P-SCH sequence in a UMTS communication system, involving the step of receiving (41) said signal including a synchronization sequence (P-SCH); performing a correlation (42) of each received sample with a known synchronization sequence (P-SCH) in order to generate a correlation profile; determining (43) the level of noise and computing a first threshold; suppressing (44) any peaks within said correlation profile having a magnitude inferior to said first threshold; detecting (45) the persistent local maximum peaks over a period of N slots; applying a predetermined mask positioned with respect to said persistent peaks and associated to at least one second threshold value distinctive from said first threshold.
摘要翻译：一种用于在UMTS通信系统中实现P-SCH序列的时隙同步的过程，包括接收（41）包括同步序列（P-SCH）的所述信号的步骤; 以已知同步序列（P-SCH）来执行每个接收样本的相关（42），以便产生相关分布; 确定（43）噪声水平并计算第一阈值; 抑制（44）所述相关曲线内具有低于所述第一阈值的幅度的任何峰值; 在N个时隙的周期内检测（45）持续局部最大峰值; 施加相对于所述持久峰定位的预定掩模并且与与所述第一阈值不同的至少一个第二阈值相关联。

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