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41. 发明申请

US20180285375A1 MINIMIZING FILE CREATION AND ACCESS TIMES USING SKIP OPTIMIZATION 审中-公开
公开(公告)号：US20180285375A1
公开(公告)日：2018-10-04
申请号：US15666606
申请日：2017-08-02
申请人： VMWARE, INC.
发明人： ASIT DESAI , BRYAN BRANSTETTER , PRASANNA AlTHAL , PRASAD RAO JANGAM , MAHESH S. HIREGOUDAR , ROHAN PASALKAR
IPC分类号： G06F17/30 , G06F12/02 , G06F12/1036
CPC分类号： G06F16/13 , G06F12/023 , G06F12/1036 , G06F16/1727 , G06F2212/1044 , G06F2212/65
摘要： Exemplary methods, apparatuses, and systems determine whether a skip optimization process can be used to store a file in a storage space. When it is determined that the skip optimization can be performed, a file stored in the storage space can be referenced in a file metadata data structure using direct addressing of file blocks storing the file instead of through indirect addressing (e.g., pointer addresses stored in pointer blocks).

42. 发明授权

US10078597B2 System and method of distinguishing system management mode entries in a translation address cache of a processor 有权
公开(公告)号：US10078597B2
公开(公告)日：2018-09-18
申请号：US14678600
申请日：2015-04-03
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： Viswanath Mohan
IPC分类号： G06F12/10 , G06F12/1036
CPC分类号： G06F12/1036 , G06F2212/684
摘要： A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.

43. 发明授权

US10062137B2 Communication between integrated graphics processing units 有权
公开(公告)号：US10062137B2
公开(公告)日：2018-08-28
申请号：US15121217
申请日：2014-02-27
申请人： Hewlett Packard Enterprise Development LP
发明人： Indrajit Roy , Sangman Kim , Vanish Talwar
IPC分类号： G06T1/20 , G06F15/167 , G06F9/50 , G06F12/04 , G06F12/1009 , G06F12/1036 , G06T1/60
CPC分类号： G06T1/20 , G06F9/50 , G06F12/04 , G06F12/1009 , G06F12/1036 , G06F12/1072 , G06F15/167 , G06F2212/656 , G06F2212/657 , G06T1/60
摘要： The communication between integrated graphics processing units (GPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated GPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

44. 发明授权

US10025726B2 Method in a memory management unit for managing address translations in two stages 有权
公开(公告)号：US10025726B2
公开(公告)日：2018-07-17
申请号：US14526686
申请日：2014-10-29
申请人： STMicroelectronics International N.V.
发明人： Herve Sibert , Loic Pallardy
IPC分类号： G06F12/00 , G06F12/1036 , G06F12/1009
摘要： A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

45. 发明申请

US20180196758A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE 审中-公开
公开(公告)号：US20180196758A1
公开(公告)日：2018-07-12
申请号：US15912363
申请日：2018-03-05
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/1027 , G06F12/02 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1045 , G06F9/455
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

46. 发明申请

US20180157601A1 APPARATUS AND METHOD FOR AVOIDING CONFLICTING ENTRIES IN A STORAGE STRUCTURE 审中-公开
公开(公告)号：US20180157601A1
公开(公告)日：2018-06-07
申请号：US15370570
申请日：2016-12-06
申请人： ARM Limited
发明人： Richard F. BRYANT , Max John BATLEY , Lilian Atieno HUTCHINS , Sujat JAMIL
IPC分类号： G06F12/12 , G06F12/1036
CPC分类号： G06F12/12 , G06F12/1036
摘要： An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data. A record of the candidate entries in then maintained, and, once the portion of the new data required for conflict detection is available, the conflict detection circuitry then performs a final stage detection operation to determine whether any of the candidate entries do contain data that conflicts with the new data. Any entries identified by the final stage detection operation as containing data that conflicts with the new data are then invalidated. This provides a particularly efficient mechanism for avoiding conflicting entries in a storage structure.

47. 发明授权

US09990305B2 Memory management component having multiple memory management modules and method therefor 有权
公开(公告)号：US09990305B2
公开(公告)日：2018-06-05
申请号：US14490902
申请日：2014-09-19
申请人： Nir Baruch , Nir Atzmon , David W. Todd
发明人： Nir Baruch , Nir Atzmon , David W. Todd
IPC分类号： G06F12/1036 , G06F12/1009 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/1009 , G06F12/1441 , G06F2212/657
摘要： A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

48. 发明授权

US09971705B2 Virtual memory address range register 有权
公开(公告)号：US09971705B2
公开(公告)日：2018-05-15
申请号：US15048400
申请日：2016-02-19
申请人： Intel Corporation
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F12/10 , G06F12/109 , G06F12/1036 , G06F12/02
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

49. 发明授权

US09864680B2 Virtual storage address threshold for freemained frames 有权
公开(公告)号：US09864680B2
公开(公告)日：2018-01-09
申请号：US15292583
申请日：2016-10-13
申请人： International Business Machines Corporation
发明人： Steven M. Partlow
IPC分类号： G06F12/00 , G06F12/02 , G06F12/1036
CPC分类号： G06F12/023 , G06F3/0605 , G06F3/0631 , G06F3/0644 , G06F3/0665 , G06F3/067 , G06F12/0223 , G06F12/0646 , G06F12/08 , G06F12/1036 , G06F12/12 , G06F17/3007 , G06F17/30233 , G06F2212/1044 , G06F2212/152 , G06F2212/154 , G06F2212/50 , G06F2212/657
摘要： Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

50. 发明申请

US20170371803A1 METHOD AND APPARATUS TO ALLOW SECURE GUEST ACCESS TO EXTENDED PAGE TABLES 审中-公开
公开(公告)号：US20170371803A1
公开(公告)日：2017-12-28
申请号：US15647179
申请日：2017-07-11
申请人： Krystof C. Zmudzinski
发明人： Krystof C. Zmudzinski
IPC分类号： G06F12/1009 , G06F12/14 , G06F9/455 , G06F12/1036
摘要： An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table (EPT) mappings between a guest physical address (GPA) space and a host physical address (HPA) space; the hypervisor to create an EPT edit table and populate the EPT edit table with information related to permitted mappings between the GPA space and HPA space; a guest to read the EPT edit table to determine information related to the permitted mappings between the GPA space and HPA space, the guest to use the information to map one or more pages in the GPA space to one or more pages in the HPA space.

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