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41. 发明授权

US09305631B1 Profiling method of address access count of semiconductor device and profiling circuit using the same 有权
标题翻译：半导体器件地址访问次数分析方法及其仿真电路
公开(公告)号：US09305631B1
公开(公告)日：2016-04-05
申请号：US14107669
申请日：2013-12-16
申请人： Samsung Electronics Co., Ltd.
发明人： Young Soo Sohn , Jong Pil Son , Jae Sung Kim , Chul Woo Park
IPC分类号： G06F12/10 , G11C11/406 , G11C11/402
CPC分类号： G11C11/40607 , G06F12/1018 , G11C7/00 , G11C11/402 , G11C11/406 , G11C11/40615 , G11C11/408
摘要： Provided is a profiling unit and method for profiling a number of times that an input/output address of a semiconductor device is accessed. The profiling unit includes a hash unit configured to produce at least one hash value by perform a hash operation on the input/output address, and a profiling circuit configured to profile the number of times that the input/output address is accessed by using the at least one hash value.
摘要翻译：提供了一种用于轮廓访问半导体器件的输入/输出地址的次数的分析单元和方法。简档单元包括散列单元，其被配置为通过对输入/输出地址执行散列操作来产生至少一个散列值;以及简档电路，其被配置为通过使用at来描述输入/输出地址被访问的次数最少一个哈希值。

42. 发明授权

US09135977B2 Random access memories with an increased stability of the MOS memory cell 有权
标题翻译：具有增加的MOS存储器单元的稳定性的随机存取存储器
公开(公告)号：US09135977B2
公开(公告)日：2015-09-15
申请号：US12109329
申请日：2008-04-24
申请人： Ashok Kumar Kapoor
发明人： Ashok Kumar Kapoor
IPC分类号： H01L29/772 , H01L21/8244 , G11C11/402 , G11C11/404 , G11C11/412 , G11C16/04 , H01L27/11
CPC分类号： G11C11/4023 , G11C11/404 , G11C11/412 , G11C16/0416 , H01L27/1104
摘要： In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices.
摘要翻译：在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。这又导致存储单元的漏电流的增加。随着使用越来越多的存储单元，必须控制漏电流。公开了具有动态阈值电压控制方案的随机存取存储器，其不再对现有的MOS工艺技术进行微小的改变。所公开的发明控制MOS晶体管的阈值电压。还包括用于增强使用该装置的动态阈值控制技术的影响的方法。本发明对SRAM，DRAM和NVM器件特别有用。

43. 发明申请

US20150187406A1 ACTIVE CONTROL DEVICE, SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：主动控制装置，半导体装置和包括其的系统
公开(公告)号：US20150187406A1
公开(公告)日：2015-07-02
申请号：US14231262
申请日：2014-03-31
申请人： SK hynix Inc.
发明人： Jin Ah KIM
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/402
CPC分类号： G11C11/4076 , G11C8/12 , G11C11/402 , G11C11/40615 , G11C11/40618 , G11C11/4085
摘要： Disclosed herein are an active control device, a semiconductor device and system including the same. The active control device may include a refresh control unit configured for outputting a refresh signal by controlling a delay time for a refresh start time when a refresh operation is performed and a precharge signal generation unit configured for generating a bank precharge signal for precharging a bank in response to the refresh signal. The refresh control unit may include a refresh delay unit for delaying a bank-active signal for a specific time and outputting a delay signal, and the refresh delay unit may be operably coupled with a plurality of banks in common.
摘要翻译：这里公开了一种主动控制装置，半导体装置及包括该控制装置的系统。主动控制装置可以包括刷新控制单元，其被配置为通过控制执行刷新操作时的刷新开始时间的延迟时间来输出刷新信号;以及预充电信号生成单元，其被配置为产生用于对银行进行预充电的存储体预充电信号响应刷新信号。刷新控制单元可以包括刷新延迟单元，用于将特定时间的存储体活动信号延迟并输出延迟信号，并且刷新延迟单元可以与多个存储体共同操作地耦合。

44. 发明授权

US09036440B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09036440B2
公开(公告)日：2015-05-19
申请号：US13716418
申请日：2012-12-17
申请人： SK hynix Inc.
发明人： Choung-Ki Song
IPC分类号： G11C7/00 , G11C11/402 , G11C11/406
CPC分类号： G11C11/40607 , G11C11/402 , G11C11/40611 , G11C11/40615 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a clock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.
摘要翻译：半导体存储器件包括配置为包括多个字线的存储单元阵列，被配置为接收时钟使能信号的时钟使能缓冲器，被配置为接收多个命令的多个命令缓冲器，配置为顺序地配置的刷新控制单元在自刷新模式下激活多个字线，命令解码器，被配置为对时钟使能信号和多个命令进行解码，并允许刷新控制单元进入自刷新模式或退出自刷新模式，以及缓冲器控制单元，被配置为当所述时钟使能信号被去激活时禁用所述多个命令缓冲器，并且当所述刷新控制单元退出所述自刷新模式时启用所述多个命令缓冲器。

45. 发明授权

US08971143B2 Semiconductor device periodically updating delay locked loop circuit 有权
标题翻译：半导体器件周期性地更新延迟锁定环电路
公开(公告)号：US08971143B2
公开(公告)日：2015-03-03
申请号：US13315128
申请日：2011-12-08
申请人： Takuyo Kodama , Kosuke Goto
发明人： Takuyo Kodama , Kosuke Goto
IPC分类号： G11C11/402 , G11C8/18 , H03L7/00 , G11C7/10 , G11C7/22 , G11C11/406
CPC分类号： H03K5/13 , G11C7/1072 , G11C7/222 , G11C11/40615
摘要： Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.
摘要翻译：公开了一种这样的装置，其包括控制电路，其响应于第一命令信号输出具有第一时钟周期的第一时钟信号，并响应于第二命令信号输出具有第二时钟周期的第二时钟信号，第一电路控制基于第一时钟信号，以及基于第二时钟信号控制的第二电路。

46. 发明授权

US08964461B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08964461B2
公开(公告)日：2015-02-24
申请号：US14084386
申请日：2013-11-19
申请人： Micron Technology, Inc.
发明人： Yogesh Luthra
IPC分类号： G11C11/39 , G11C16/26 , H01L27/108 , H01L29/73 , H01L29/78 , G11C11/402 , H01L27/102
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个实施例中，技术可以被实现为用于偏置直接注入半导体存储器件的方法，包括以下步骤：通过位线将第一非负电压电位施加到第一区域，并将第二非负电压电位施加到经由源极线的第二区域。该方法还可以包括将第三电压电位施加到字线，其中字线可以与可以电浮动并且布置在第一区域和第二区域之间的体区间隔开并且电容化。该方法可以进一步包括经由载体注入管线将第四正电压电位施加到第三区域，其中第三区域可以设置在第一区域，体区域和第二区域中的至少一个之下。

47. 发明授权

US08861296B2 Memory refresh methods, memory section control circuits, and apparatuses 有权
标题翻译：存储器刷新方法，存储器部分控制电路和装置
公开(公告)号：US08861296B2
公开(公告)日：2014-10-14
申请号：US14084417
申请日：2013-11-19
申请人： Micron Technology, Inc.
发明人： John David Porter , Gi-Hong Kim
IPC分类号： G11C7/00 , G11C11/402 , G11C11/408 , G11C8/08 , G11C5/14 , G11C11/406 , G11C8/10
CPC分类号： G11C11/40615 , G11C5/147 , G11C8/08 , G11C8/10 , G11C11/402 , G11C11/406 , G11C11/4085 , G11C2211/4065 , G11C2211/4067
摘要： Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
摘要翻译：公开了设备，存储器部分控制电路和刷新存储器的方法。示例性设备包括多个存储器部分和多个存储器部分控制电路。每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。

48. 发明授权

US08854911B2 Memory and method of refreshing a memory 有权
标题翻译：内存和刷新内存的方法
公开(公告)号：US08854911B2
公开(公告)日：2014-10-07
申请号：US13743350
申请日：2013-01-17
申请人： Etron Technology, Inc.
发明人： Chun Shiah , Sen-Fu Hong
IPC分类号： G11C7/00 , G11C11/402 , G11C11/406
CPC分类号： G11C11/402 , G11C11/40603 , G11C11/40615 , G11C11/40618
摘要： A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle.
摘要翻译：存储器包括确定电路，多个刷新计数器和多个存储体。确定电路接收刷新命令。多个刷新计数器耦合到确定电路。多个刷新计数器的每个刷新计数器对应于多个存储体中的一个存储体。确定电路检测多个组的第一组是否被使能，或者由对应于第一组的多个刷新计数器的第一刷新计数器计数的数量等于预定值。然后，确定电路根据检测结果可选地刷新多个存储体中的一个存储体。因此，即使多个存储体都不是空闲，存储器仍然根据刷新命令刷新空闲存储体。

49. 发明授权

US08837246B2 Memory device, operation method thereof and memory system having the same 有权
标题翻译：存储器件，其操作方法和具有该存储器件的存储器系统
公开(公告)号：US08837246B2
公开(公告)日：2014-09-16
申请号：US13803520
申请日：2013-03-14
申请人： Samsung Electronics Co., Ltd.
发明人： Ki Heung Kim , In Chul Jeong
IPC分类号： G11C7/00 , G11C11/402 , G11C11/406
CPC分类号： G11C11/402 , G11C11/40618
摘要： A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.
摘要翻译：存储器刷新方法包括从存储器件的N个存储体中选择至少一个存储区，以及在刷新周期的L个刷新周期之一中激活包括在所述至少一个存储体中的多个字线中的K个字线。每个N个组包括M个字线，N，K和M各自是大于或等于2的自然数，L是小于或等于M的自然数，K等于M * N / L。

50. 发明授权

US08811099B2 Period signal generation circuits 有权
标题翻译：周期信号发生电路
公开(公告)号：US08811099B2
公开(公告)日：2014-08-19
申请号：US13716034
申请日：2012-12-14
申请人： SK hynix Inc.
发明人： Dong Kyun Kim
IPC分类号： G11C7/22 , G11C11/402 , G11C5/14 , G11C11/406 , G11C7/00
CPC分类号： G11C11/4023 , G11C5/147 , G11C7/00 , G11C11/406 , G11C11/40615 , G11C11/40626
摘要： A period signal generation circuit includes a period signal generator configured to alternately charge and discharge a control node according to a level of the control node to generate a period signal, a discharge controller configured to discharge a first current having a constant value from the control node in response to a temperature signal and discharge a second current varying according to an internal temperature thereof from the control node in response to the temperature signal, and a tester configured to control a charging speed and a discharging speed of the control node.
摘要翻译：周期信号生成电路包括周期信号发生器，被配置为根据控制节点的电平交替地对控制节点进行充电和放电以产生周期信号;放电控制器，被配置为从控制节点放电具有恒定值的第一电流响应于温度信号，并且响应于温度信号，从控制节点排出根据其内部温度而变化的第二电流，以及被配置为控制控制节点的充电速度和放电速度的测试器。

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