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1. 发明授权

US10083734B1 Memory arrays 有权
公开(公告)号：US10083734B1
公开(公告)日：2018-09-25
申请号：US15804981
申请日：2017-11-06
申请人： Micron Technology, Inc.
发明人： Sanh D. Tang , Kuo-Chen Wang , Martin C. Roberts , Diem Thy N. Tran , Hideki Gomi , Fredrick D. Fishburn , Srinivas Pulugurtha , Michel Koopmans , Eiji Hasunuma
IPC分类号： G11C11/24 , G11C11/402 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4023 , G11C5/025 , G11C5/063 , G11C8/14 , G11C11/4097 , G11C2207/105 , H01L27/10805 , H01L27/10814 , H01L27/10847 , H01L27/10855 , H01L27/10885
摘要： Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

2. 发明申请

US20180130515A1 APPARATUSES AND METHODS FOR COMPUTE COMPONENTS FORMED OVER AN ARRAY OF MEMORY CELLS 审中-公开
公开(公告)号：US20180130515A1
公开(公告)日：2018-05-10
申请号：US15806123
申请日：2017-11-07
申请人： Micron Technology, Inc.
发明人： Jason T. Zawodny
IPC分类号： G11C11/402 , G11C11/403 , G11C11/406
CPC分类号： G11C11/4023 , G11C5/025 , G11C7/1006 , G11C11/402 , G11C11/403 , G11C11/406 , G11C11/407 , G11C2211/4068
摘要： The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

3. 发明授权

US09147459B2 Dynamic random access memories with an increased stability of the MOS memory cells 有权
标题翻译：具有增加的MOS存储器单元的稳定性的动态随机存取存储器
公开(公告)号：US09147459B2
公开(公告)日：2015-09-29
申请号：US12610895
申请日：2009-11-02
申请人： Ashok Kumar Kapoor
发明人： Ashok Kumar Kapoor
IPC分类号： H01L29/94 , H01L27/108 , G11C11/402 , G11C11/404 , G11C11/412 , G11C16/04 , H01L27/11
CPC分类号： G11C11/4023 , G11C11/404 , G11C11/412 , G11C16/0416 , H01L27/1104
摘要： In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.
摘要翻译：在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。这又导致存储单元的漏电流的增加。随着使用越来越多的存储单元，必须控制漏电流。公开了具有动态阈值电压控制方案的随机存取存储器，其不再对现有的MOS工艺技术进行微小的改变。所公开的发明控制MOS晶体管的阈值电压。还包括用于增强使用该装置的动态阈值控制技术的影响的方法。本发明对DRAM和NVM器件特别有用。

4. 发明授权

US06560136B1 Single-port memory cell 有权
标题翻译：单端口存储单元
公开(公告)号：US06560136B1
公开(公告)日：2003-05-06
申请号：US09806395
申请日：2001-06-12
申请人： Jain Raj Kumar
发明人： Jain Raj Kumar
IPC分类号： G11C1700
CPC分类号： G11C11/4023 , G11C11/404
摘要： A single-port memory cell arrangement includes a multiplicity of single-port memory cells, each having a selection transistor and a memory transistor. The selection transistor has a control terminal connected to a word line, and a load-path connected to a data line. The memory transistor has a control terminal connected to a supply potential, and a load-path connected to the second end of the selection-transistor's load-path. The memory transistor is configured to switch, in response to a signal on the data line, between first and second potentials corresponding to two memory states. These potentials and the supply potential are selected such that first and second ends of the memory-transistor-load-path are at the same potential. The memory cell also includes a controllable switch having a first terminal connected to a supply line, and a second terminal connected to the second end of the memory-transistor-load-path. A single charging device assigned to the single-port memory cells provides providing a precharging potential. From time to time, the charging device recharges a selected memory transistor through the supply line and a selected controllable switch corresponding to that memory transistor.
摘要翻译：单端口存储单元布置包括多个单端口存储单元，每个具有选择晶体管和存储晶体管。选择晶体管具有连接到字线的控制端子和连接到数据线的负载路径。存储晶体管具有连接到电源电位的控制端子和连接到选择晶体管的负载路径的第二端的负载路径。存储晶体管被配置为响应于数据线上的信号在对应于两个存储器状态的第一和第二电位之间切换。选择这些电位和电源电位使得存储晶体管负载路径的第一和第二端处于相同的电位。存储单元还包括具有连接到电源线的第一端子和连接到存储器 - 晶体管负载路径的第二端的第二端子的可控开关。分配给单端口存储单元的单个充电装置提供预充电潜力。有时，充电装置通过供电线路和对应于该存储晶体管的选择的可控开关对选定的存储晶体管充电。

5. 发明申请

US20020075723A1 METHOD FOR OPERATING A MEMORY CELL CONFIGURATION HAVING DYNAMIC GAIN MEMORY CELLS 有权
标题翻译：用于操作具有动态增益记忆细胞的记忆细胞配置的方法
公开(公告)号：US20020075723A1
公开(公告)日：2002-06-20
申请号：US09935356
申请日：2001-08-22
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlosser , Josef Willer
IPC分类号： G11C011/36
CPC分类号： G11C11/404 , G11C11/4023
摘要： Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
摘要翻译：单元结构的每个存储单元包括至少一个存储晶体管。为了在存储单元上写入第一或第二信息，对存储晶体管的栅电极进行充电，使得在存储晶体管中施加第一电压或第二电压。在存储晶体管的第二源极/漏极区域中施加读取电压以分别读取第一信息和第二信息。第一电压施加在第二电压和读取电压之间。读取电压施加在较低存储晶体管的阈值电压的第一电压和小于存储晶体管的阈值电压的第二电压之间。

6. 发明授权

US4203159A Pseudostatic electronic memory 失效
标题翻译：伪静电电子记忆体
公开(公告)号：US4203159A
公开(公告)日：1980-05-13
申请号：US948683
申请日：1978-10-05
申请人： Frank M. Wanlass
发明人： Frank M. Wanlass
IPC分类号： G11C11/402 , G11C7/00 , G11C11/24
CPC分类号： G11C11/402 , G11C11/4023
摘要： An electronic memory is described which has only two transistors in each memory cell, but does not require that data processing be periodically interrupted to enable refreshing. It adds to a typical, single transistor cell dynamic memory one additional transistor per cell, and a duplication of the driving and sensing circuitry typically included in such a memory. The additional transistor in each cell provides access to the same for refreshing, which refreshing is accomplished by the additional driving and sensing circuitry at the very same time the memory is otherwise being accessed for data processing.
摘要翻译：描述了在每个存储器单元中仅具有两个晶体管的电子存储器，但不要求周期性地中断数据处理以实现刷新。它增加了典型的单晶体管单元动态存储器，每个单元一个附加晶体管，以及通常包括在这种存储器中的驱动和感测电路的复制。每个单元中的附加晶体管提供对其的访问以进行刷新，该刷新在附加的驱动和感测电路实现的同时，存储器另外被存取用于数据处理。

7. 发明授权

US4035782A Charge coupled device circuit for use with a semiconductor Storage Unit or a semiconductor Logical Unit 失效
标题翻译：用于半导体存储单元或半导体逻辑单元的电荷耦合器件电路
公开(公告)号：US4035782A
公开(公告)日：1977-07-12
申请号：US590275
申请日：1975-06-25
申请人： Karl Goser
发明人： Karl Goser
IPC分类号： G11C11/402 , G11C11/403 , G11C11/404 , H01L27/07 , H01L27/105 , H03K3/356 , G11C11/44
CPC分类号： H01L27/1057 , G11C11/4023 , G11C11/403 , G11C11/404 , H01L27/0705 , H03K3/356 , H03K3/356052
摘要： A charge coupled device circuit for use with a semiconductor Storage Unit or a semiconductor Logical Unit which includes at least a charge coupled device serially connected with a transistor between a supply voltage line and a reference potential (such as ground). The charge coupled device is located between the supply voltage line and the transistor. A further embodiment of the present invention includes, in addition to the above, a second transistor connected to form a flip-flop with the first transistor. A second charge coupled device is connected serially to the second transistor and in turn to the reference potential. The charge coupled device of this invention includes at least three control electrodes. A first electrode of each charge coupled device are connected to each other and to a first pulse line. A third electrode of each charge coupled device are connected to each other and to a second pulse line. The second electrode of the first charge coupled device is connected to the gate electrode of the second transistor and to a first selection transistor. The second electrode of the second charge coupled device is connected to the gate electrode of the first transistor and to a second selection transistor. The transistors referred to are field effect transistors having source, drain and gate electrodes.Another embodiment of the invention includes a storage capacitor connected between the midpoint of the serially connected charge coupled device and its associated transistor and ground.
摘要翻译：一种与半导体存储单元或半导体逻辑单元一起使用的电荷耦合器件电路，其至少包括与电源电压线和参考电位（例如地）之间的晶体管串联连接的电荷耦合器件。电荷耦合器件位于电源电压线和晶体管之间。除了上述之外，本发明的另一实施例还包括连接到与第一晶体管形成触发器的第二晶体管。第二电荷耦合器件串联连接到第二晶体管，并依次连接到参考电位。本发明的电荷耦合器件包括至少三个控制电极。每个电荷耦合器件的第一电极彼此连接并连接到第一脉冲线。每个电荷耦合器件的第三电极彼此连接并连接到第二脉冲线。第一电荷耦合器件的第二电极连接到第二晶体管的栅电极和第一选择晶体管。第二电荷耦合器件的第二电极连接到第一晶体管的栅电极和第二选择晶体管。所指的晶体管是具有源极，漏极和栅电极的场效应晶体管。

8. 发明授权

US3870901A Method and apparatus for maintaining the charge on a storage node of a mos circuit 失效
标题翻译：用于维护MOS电路存储节点上的电荷的方法和装置
公开(公告)号：US3870901A
公开(公告)日：1975-03-11
申请号：US42342273
申请日：1973-12-10
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F , HUBER ROBERT J
IPC分类号： G11C11/402 , G11C11/406 , G11C11/412 , G11C11/417 , H01L21/822 , H01L27/04 , H03K3/356 , H03K17/00 , H03K17/24 , H03K3/286 , G11C11/38 , H03K3/33
CPC分类号： G11C11/417 , G11C11/4023 , G11C11/406 , G11C11/412 , H03K3/356 , H03K3/356052 , H03K3/356104 , H03K17/24 , H03K2217/0036
摘要： Method and apparatus for maintaining the charge on a storage node of a MOS circuit of the type having a depletion mode transistor as a load resistor situated between a voltage source and a storage node. The voltage level of the storage node determines the output of the circuit. The storage node is charged to a first voltage level upon the receipt of a given data input to the circuit. The substrate of the circuit is reversed biased to a level sufficient to render the depletion mode transistor nonconducting. This will isolate the storage node and isolation will continue for a time selected to maintain a residual charge of a given magnitude on the storage node if the node was originally charged. The substrate bias is removed to permit the depletion mode transistor to again become conductive. If the residual charge was present on the storage node, the node is permitted to recharge thus returning the node to the first voltage level and re-establishing the output of the circuit. In this way power consumption is minimized while the state of the circuit is maintained.
摘要翻译：用于将具有耗尽型晶体管的MOS电路的存储节点上的电荷维持为位于电压源和存储节点之间的负载电阻器的方法和装置。存储节点的电压电平决定电路的输出。在接收到输入到电路的给定数据时，存储节点被充电到第一电压电平。电路的衬底被反向偏置到足以使耗尽型晶体管不导通的电平。这将隔离存储节点，并且如果节点最初被充电，则隔离将在所选择的时间内持续一段时间以保持存储节点上的给定幅度的剩余电荷。去除衬底偏置以使耗尽型晶体管再次变成导电。如果存储节点上存在剩余电荷，则允许节点进行充电，从而将节点返回到第一电压电平并重新建立电路的输出。以这种方式，电力消耗被最小化，同时维持电路的状态。

9. 发明授权

US3706975A High speed mos random access memory 失效
标题翻译：高速MOS随机存取存储器
公开(公告)号：US3706975A
公开(公告)日：1972-12-19
申请号：US3706975D
申请日：1970-10-09
申请人： TEXAS INSTRUMENTS INC
发明人： PALUCK ROBERT J
IPC分类号： G11C11/402 , G11C11/408 , G11C11/40
CPC分类号： G11C11/4087 , G11C11/4023
摘要： Disclosed is a high speed insulated gate field effect transistor random access memory circuit integrated on a monolithic chip. The memory circuit utilizes a low voltage decoding circuit that is compatible with transistor-transistor-logic circuit output levels, enabling a reduction in the number of discrete MOS devices required for each memory cell. Also disclosed is a novel method for decoding wherein all of the lines of the memory matrix are brought high at the start of each cycle, recharging the internal capacitance of all of the memory cells of the matrix. All of the undesired lines of the memory matrix are then discharged through an OR circuit arrangement connected in series with each line, thereby disconnecting all but a preselected cell of the memory matrix from the computer input/output sense lines.
摘要翻译：公开了集成在单片芯片上的高速绝缘栅场效应晶体管随机存取存储器电路。存储器电路利用与晶体管 - 晶体管逻辑电路输出电平兼容的低电压解码电路，能够减少每个存储单元所需的离散MOS器件的数量。还公开了一种新颖的解码方法，其中存储矩阵的所有行在每个周期开始时变高，对矩阵的所有存储单元的内部电容进行再充电。存储器矩阵的所有不期望的行然后通过与每行串联连接的OR电路布局放电，从而从存储器矩阵的预选单元与计算机输入/输出感测线分离。

10. 发明授权

US3644907A Complementary mosfet memory cell 失效
标题翻译：补充MOSFET存储单元
公开(公告)号：US3644907A
公开(公告)日：1972-02-22
申请号：US3644907D
申请日：1969-12-31
申请人： WESTINGHOUSE ELECTRIC CORP
发明人： GRICCHI JAMES R , HUDSON JAMES R
IPC分类号： G11C11/402 , G11C11/412 , H03K3/356 , G11C11/40 , G11C5/02 , G11C7/00
CPC分类号： G11C11/412 , G11C11/4023 , H03K3/356104
摘要： A semiconductor read/write memory array and memory cell therefore including complementary metal oxide semiconductor field-effect transistors (MOSFETs) coupled together as a first and a second inverter circuit with direct cross-coupled connections therebetween for providing a flip-flop circuit. Each bit of the memory array is comprised of at least five MOSFET devices operated from a single clocked power supply source wherein four of the MOSFET devices are operated as complementary pairs to comprise the first and second inverters. The flip-flop circuit is clocked or pulsed for turning the MOSFET devices ''''off'''' of one of the inverters referred to as the output inverter to trap an electrical charge at one of the circuit nodes in order to obtain a high input impedance so that the state of the cell can be changed when addressed or alternatively to preset the logic output state of the memory cell. The memory cell is coupled to a common input/output digit data line and an address line of the memory array by means of a selection switch MOSFET so that data is written into and read out of the memory cell on the same digit data line through the selection switch MOSFET when turned ''''on'''' by means of a signal applied to the address line. Furthermore, nondestructive readout of the state of the memory cell when addressed is achieved by precharging the digit data line to a predetermined potential prior to the energization of the selection switch MOSFET during the read mode.

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