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41. 发明申请

US20160111061A1 LOW POWER HIGH FREQUENCY DIGITAL PULSE FREQUENCY MODULATOR 有权
标题翻译：低功率高频数字脉冲频率调制器
公开(公告)号：US20160111061A1
公开(公告)日：2016-04-21
申请号：US14129269
申请日：2013-06-10
申请人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
发明人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
IPC分类号： G09G5/00 , H03K17/284 , G06F3/041 , H03K7/06 , H02M3/158 , H03K5/14 , H03K7/08
CPC分类号： G09G5/006 , G06F3/0412 , G09G2330/021 , H02M3/158 , H02M3/1584 , H02M2001/0009 , H02M2001/0032 , H02M2003/1586 , H03K5/14 , H03K7/06 , H03K7/08 , H03K17/284 , Y02B70/16
摘要： Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.
摘要翻译：描述了一种装置，包括：可编程延迟线（PDL），用于接收作为输入的脉宽调制（PWM）信号并产生第一输出; 选择单元，其可操作以提供PWM信号或其反相版本作为第二输出; 以及连接到PDL的顺序单元，该顺序单元用第一输出对第二输出进行采样，该顺序单元用于产生脉冲 - 频率调制（PFM）输出。还描述了一种电压调节器，其包括：用于耦合到负载的相互耦合的片上电感器; 耦合到相互耦合的片上电感器的桥，包括低侧开关和高侧开关; PWM控制器，用于在第一负载电流期间控制所述低侧和高侧开关; 以及PFM控制器，用于在第二负载电流期间控制低侧和高侧开关，所述第二负载电流小于所述第一负载电流，所述PFM控制器包括：比较器，用于将所述负载的输出电压与参考电压; 以及耦合到比较器的用于确定高侧开关的导通持续时间的第一PDL。

42. 发明申请

US20160105106A1 CONTROLLER AND POWER CONVERTER USING THE SAME 审中-公开
标题翻译：使用相同的控制器和电源转换器
公开(公告)号：US20160105106A1
公开(公告)日：2016-04-14
申请号：US14878648
申请日：2015-10-08
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Hyun Ku KANG
IPC分类号： H02M3/156 , H03K17/284 , H03K17/60 , H03K5/24 , H02M1/08 , H03K17/687
CPC分类号： H02M3/156 , H02M1/08 , H02M2001/0025 , H03K5/24 , H03K17/284 , H03K17/60 , H03K17/687
摘要： The object of the present invention is to provide a controller, and a power converter using the same, which can expand the range of a voltage applied to a load.The present invention provides a controller, which includes a switch signal unit configured to output a control signal repeating a high state and a low state by receiving a first signal and a second signal, a first signal generation unit configured to generate the first signal, and configured to transmit the first signal to the switch signal unit, and a second signal generation unit configured to generate the second signal by comparing a sensing voltage and a variable first reference voltage, and configured to transmit the second signal to the switch signal unit, wherein the first signal generation unit is configured to adjust a transmission time of the first signal by sensing a voltage level of the first reference voltage, and a power converter using the same.
摘要翻译：本发明的目的是提供一种控制器和使用该控制器的功率转换器，其可以扩展施加到负载的电压的范围。本发明提供了一种控制器，其包括：开关信号单元，被配置为通过接收第一信号和第二信号来输出重复高状态和低状态的控制信号;第一信号生成单元，被配置为产生第一信号;以及被配置为将第一信号发送到开关信号单元，以及第二信号生成单元，被配置为通过比较感测电压和可变的第一参考电压来生成第二信号，并且被配置为将第二信号发送到开关信号单元，其中第一信号生成单元被配置为通过感测第一参考电压的电压电平来调节第一信号的传输时间，以及使用其的功率转换器。

43. 发明申请

US20160020756A1 Delay Line System and Switching Apparatus with Embedded Attenuators 有权
标题翻译：具有嵌入式衰减器的延迟线系统和开关装置
公开(公告)号：US20160020756A1
公开(公告)日：2016-01-21
申请号：US14709000
申请日：2015-05-11
申请人： Peregrine Semiconductor Corporation
发明人： Raul Inocencio Alidio , Peter Bacon
IPC分类号： H03K5/08 , H03K17/76 , H03K17/284
CPC分类号： H03K5/133 , H03K5/14 , H03K17/28 , H03K17/284
摘要： Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators.
摘要翻译：描述了用于降低延迟线模块之间的驻波反射的系统，方法和装置。延迟线模块包括半导体开关，特别是在绝缘体上硅（“SOI”）和硅 - 蓝宝石（“SOS”）衬底和嵌入式衰减器上制造的MOSFET开关。

44. 发明授权

US09203382B2 Integrated clock gater (ICG) using clock cascode complimentary switch logic 有权
标题翻译：集成时钟门控器（ICG），采用时钟共源共栅开关逻辑
公开(公告)号：US09203382B2
公开(公告)日：2015-12-01
申请号：US14613349
申请日：2015-02-03
申请人： Matthew S. Berzins , Prashant U. Kenkare
发明人： Matthew S. Berzins , Prashant U. Kenkare
IPC分类号： H03K17/284 , H03K3/356 , H03K19/00 , H03K19/096
CPC分类号： H03K17/284 , H03K3/356 , H03K3/356104 , H03K19/00 , H03K19/0016 , H03K19/0963 , H03K19/0966
摘要： Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.
摘要翻译：发明方面包括具有时钟互补电压开关逻辑（CICG）的集成时钟门控（ICG）电路，其提供高性能，同时保持低功耗特性。 CICG电路提供小的启用建立时间和小的时钟到使能时钟延迟。在启用和禁用模式下都能实现时钟功耗的显着降低，特别是在禁用模式下。不依赖于接收到的时钟信号的电压电平以及是否使能信号被断言，免费锁存器串联工作以在不同节点处锁存不同的电压电平。逆变器从其中一个节点获取电压电平，将其反相，并输出门控时钟信号。取决于各种电压电平，门控时钟信号可能是有源或静态的。时间从评估窗口“借”，并添加到建立时间，以提供更大的公差来接收使能信号。

45. 发明授权

US08975949B2 Integrated clock gater (ICG) using clock cascode complimentary switch logic 有权
公开(公告)号：US08975949B2
公开(公告)日：2015-03-10
申请号：US13831500
申请日：2013-03-14
申请人： Matthew S. Berzins , Prashant U. Kenkare
发明人： Matthew S. Berzins , Prashant U. Kenkare
IPC分类号： H03K17/284
CPC分类号： H03K17/284 , H03K3/356 , H03K3/356104 , H03K19/00 , H03K19/0016 , H03K19/0963 , H03K19/0966
摘要： Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

46. 发明申请

US20150015321A1 Circuit and Method for Controlling Charge Injection in Radio Frequency Switches 有权
标题翻译：射频开关电荷注入控制电路及方法
公开(公告)号：US20150015321A1
公开(公告)日：2015-01-15
申请号：US14257808
申请日：2014-04-21
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： Alexander Dribinsky , Tae Youn Kim , Dylan J. Kelly , Christopher N. Brindle
IPC分类号： H03K17/284 , H03K17/689 , H03K17/687
CPC分类号： H03K17/161 , H03K17/04 , H03K17/06 , H03K17/08 , H03K17/102 , H03K17/284 , H03K17/6874 , H03K17/689 , H03K2217/0009
摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.
摘要翻译：公开了一种用于控制电路中的电荷注入的电路和方法。在一个实施例中，电路和方法用于绝缘体上半导体（SOI）射频（RF）开关中。在一个实施例中，SOI RF开关包括串联耦合的多个开关晶体管，被称为“堆叠”晶体管，并且在SOI衬底上被实现为单片集成电路。电荷注入控制元件被耦合以从位于开关晶体管之间的电阻隔离节点接收注入的电荷，并且将注入的电荷传送到不被电阻隔离的至少一个节点。在一个实施例中，电荷注入控制元件包括电阻器。在另一个实施例中，电荷注入控制元件包括晶体管。公开了一种用于控制开关电路中的电荷注入的方法，其中注入的电荷在串联耦合的开关晶体管之间的电阻隔离节点处产生，并且注入的电荷被传送到不被电阻隔离的开关电路的至少一个节点。

47. 发明申请

US20140266396A1 INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC 有权
标题翻译：集成时钟控制（ICG）使用时钟CASCODE COMPLIMENTARY SWITCH LOGIC
公开(公告)号：US20140266396A1
公开(公告)日：2014-09-18
申请号：US13831500
申请日：2013-03-14
申请人： Matthew S. Berzins , Prashant U. Kenkare
发明人： Matthew S. Berzins , Prashant U. Kenkare
IPC分类号： H03K17/284
CPC分类号： H03K17/284 , H03K3/356 , H03K3/356104 , H03K19/00 , H03K19/0016 , H03K19/0963 , H03K19/0966
摘要： Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.
摘要翻译：发明方面包括具有时钟互补电压开关逻辑（CICG）的集成时钟门控（ICG）电路，其提供高性能，同时保持低功耗特性。 CICG电路提供小的启用建立时间和小的时钟到使能时钟延迟。在启用和禁用模式下都能实现时钟功耗的显着降低，特别是在禁用模式下。不依赖于接收到的时钟信号的电压电平以及是否使能信号被断言，不同的锁存器串联工作来锁存不同节点的不同电压电平。逆变器从其中一个节点获取电压电平，将其反相，并输出门控时钟信号。取决于各种电压电平，门控时钟信号可能是有源或静态的。时间从评估窗口“借”，并添加到建立时间，以提供更大的公差来接收使能信号。

48. 发明申请

US20140118052A1 SHIFT REGISTER AND GATE DRIVING CIRCUIT THEREOF 有权
标题翻译：移位寄存器和门驱动电路
公开(公告)号：US20140118052A1
公开(公告)日：2014-05-01
申请号：US13778063
申请日：2013-02-26
申请人： AU OPTRONICS CORP.
发明人： Li-Wei Liu , Tsung-Ting Tsai
IPC分类号： G11C19/28 , H03K17/284
CPC分类号： G11C19/28 , H03K5/15093
摘要： An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal.
摘要翻译：第N移位寄存器包括上拉单元，驱动单元，第一下拉单元，第二下拉单元和第三下拉单元。上拉单元用于根据第一时钟信号，第二时钟信号和起始脉冲提供第一上拉信号。驱动单元用于根据第一上拉信号提供驱动信号，并根据第一时钟信号和驱动信号提供门信号。第一个下拉单元用于根据第一个时钟信号拉低第一个上拉信号。第二下拉单元用于根据第二上拉信号来拉下驱动信号。第三个下拉单元用于根据第二个时钟信号来拉下门信号。

49. 发明申请

US20120319733A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120319733A1
公开(公告)日：2012-12-20
申请号：US13473826
申请日：2012-05-17
申请人： Atsushi KOBAYASHI
发明人： Atsushi KOBAYASHI
IPC分类号： H03K19/20 , H03K17/284
CPC分类号： H03K17/284 , H02M7/538 , H02M2001/0051 , H03K5/1534 , H03K17/164 , H03K19/00346 , Y02B70/1491
摘要： A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time.
摘要翻译：半导体器件包括两个单元电路和一个控制单元。单元电路之间的中间点与感性负载耦合。每个单元电路包括与第一开关元件反并联耦合的第一开关元件和续流二极管。至少一个单元电路还包括与第一开关元件和续流二极管并联耦合的旁路部分。旁路部分包括串联耦合的第二开关元件和电阻器。控制器交替地以第一开关元件关闭的死区时间来接通第一开关元件。当第一开关元件中的一个在死区时间中从断开状态转换到导通状态时，控制器控制与第一开关元件中的一个并联耦合的第二开关元件为导通状态。

50. 发明申请

US20120057387A1 HYBRID SWITCH FOR RESONANT POWER CONVERTERS 有权
标题翻译：谐振电源转换器混合开关
公开(公告)号：US20120057387A1
公开(公告)日：2012-03-08
申请号：US13206846
申请日：2011-08-10
申请人： Jih-Sheng Lai , Wensong Yu
发明人： Jih-Sheng Lai , Wensong Yu
IPC分类号： H02M7/5387 , H03K17/567 , H02M7/00 , H02M7/537 , H03K17/284 , H03K17/687
CPC分类号： H02M7/797 , H02M2001/0048 , H03K17/06 , H03K17/12 , H03K17/164 , H03K17/168 , H03K17/567 , Y02B70/1441 , Y02B70/1491
摘要： A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.
摘要翻译：包括两个并联连接但具有作为电流的函数的不同电压降特性的半导体开关的混合开关有助于实现零电压切换，并且减少传导损耗以补偿通过诸如大电流的功率转换器中的零电压切换实现的开关损耗的降低逆变器。

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