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41. 发明授权

US08846470B2 Metal trench capacitor and improved isolation and methods of manufacture 有权
标题翻译：金属沟槽电容器和改进的隔离和制造方法
公开(公告)号：US08846470B2
公开(公告)日：2014-09-30
申请号：US13153538
申请日：2011-06-06
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/8242 , H01L49/02 , H01L21/762 , H01L29/66 , H01L21/74 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/743 , H01L21/76283 , H01L27/0629 , H01L27/108 , H01L27/1087 , H01L27/1203 , H01L28/60 , H01L28/92 , H01L29/0649 , H01L29/66181
摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
摘要翻译：提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

42. 发明授权

US08835248B2 Method for forming metal wire 有权
标题翻译：金属线形成方法
公开(公告)号：US08835248B2
公开(公告)日：2014-09-16
申请号：US13480154
申请日：2012-05-24
申请人： Naoki Takeguchi
发明人： Naoki Takeguchi
IPC分类号： H01L21/8242
CPC分类号： H01L21/76838 , C23C14/16 , C23C16/06 , H01L21/28273 , H01L21/2855 , H01L21/28556 , H01L21/76876 , H01L21/76877 , H01L27/11524
摘要： Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
摘要翻译：公开了在半导体系统中制造金属线的技术。金属可以是钨。可以使用混合化学气相沉积（CVD）/物理气相沉积（PVD）工艺。可以使用CVD形成钨层。该CVD层可以形成在阻挡层上，例如但不限于TiN或WN。该CVD层可以完全填充一些特征，例如沟槽或通孔。然后，可以使用PVD在CVD层上形成钨层。然后可以蚀刻钨层以形成线或线。使用混合CVD / PVD方法形成金属线的技术可以提供具有阻挡金属的低电阻率，低表面粗糙度和良好的间隙填充。

43. 发明授权

US08828821B2 Fabrication of semiconductor stacks with ruthenium-based materials 有权
标题翻译：用钌基材料制造半导体叠层
公开(公告)号：US08828821B2
公开(公告)日：2014-09-09
申请号：US13395071
申请日：2009-09-18
申请人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/8242 , H01L21/02 , C23C16/455 , C23C16/02 , H01L27/108 , H01L49/02 , C23C16/40
CPC分类号： C23C16/45531 , C23C16/0272 , C23C16/0281 , C23C16/405 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/0228 , H01L21/02304 , H01L27/10852 , H01L28/40 , H01L28/65 , H01L28/75
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).
摘要翻译：本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。特别地，要生长电介质层的底部电极可以具有钌基表面。钌表面与电介质层的晶格匹配（例如氧化钛，钛酸锶钛酸钡或钛酸钡锶）有助于促进金红石相二氧化钛的生长，从而导致更高的介电常数和更低的有效氧化物厚度。钌基材料还提供高功函数材料，导致较低的泄漏。为了减轻与使用钌有关的成核延迟，可以采用基于钛的粘附层或胶层。可以进一步采用预处理工艺，以增加有效的电容器板面积，从而进一步提高介电常数和有效的氧化物厚度（“EOT”）。

44. 发明授权

US08815695B2 Methods to improve leakage for ZrO2 based high K MIM capacitor 有权
标题翻译：改善ZrO2基高K MIM电容器泄漏的方法
公开(公告)号：US08815695B2
公开(公告)日：2014-08-26
申请号：US13727898
申请日：2012-12-27
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Xiangxin Rui , Mitsuhiro Horikawa , Hiroyuki Ode , Karthik Ramani
IPC分类号： H01L21/02 , H01L27/108 , H01L29/92 , H01L21/8242 , H01L21/316 , H01L27/04 , H01L49/02
CPC分类号： H01L28/40 , H01L28/56 , H01L28/65 , H01L28/75
摘要： A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
摘要翻译：形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

45. 发明授权

US08779490B2 DRAM with dual level word lines 有权
标题翻译： DRAM具有双电平字线
公开(公告)号：US08779490B2
公开(公告)日：2014-07-15
申请号：US13551766
申请日：2012-07-18
申请人： Babar A. Khan , Effendi Leobandung
发明人： Babar A. Khan , Effendi Leobandung
IPC分类号： H01L27/108 , H01L29/94 , H01L29/66 , H01L21/8242 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/10867 , H01L21/84 , H01L27/0207 , H01L27/10891 , H01L27/1203 , H01L29/945
摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.
摘要翻译：深沟槽电容器上的顶部半导体层和导电帽结构通过蚀刻同时构图。导电盖结构的每个图案化部分构成导电盖结构，其横向接触作为顶部半导体层的图案化剩余部分之一的半导体材料部分。栅电极形成为不互连的离散结构。在接触电介质层的形成和平坦化之后，通过栅极线形成在接触电介质层上方的线路电平以提供与栅电极的电连接。彼此电连接的栅极电极和通过栅极线构成跨越两个电平存在的栅极线。

46. 发明授权

US08765548B2 Capacitors and methods of manufacture thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08765548B2
公开(公告)日：2014-07-01
申请号：US14017022
申请日：2013-09-03
申请人： Infineon Technologies AG
发明人： Martin Ostermayr , Richard Lindsay
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/11 , H01L27/1104 , H01L29/94
摘要： Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.
摘要翻译：公开了半导体器件，电容器及其制造方法。在一个实施例中，制造电容器的方法包括在工件上形成第一材料，并对第一材料进行构图，在工件的第一区域中形成第一电容器板，并在工件的第二区域中形成第一元件。第二材料形成在工件上面和图案化的第一材料上。图案化第二材料，在第一电容器板上的工件的第一区域中形成电容器电介质和第二电容器板，并在工件的第三区域中形成第二元件。

47. 发明授权

US08765535B2 Method for manufacturing a capacitor having a yttrium oxide layer 失效
标题翻译：具有氧化钇层的电容器的制造方法
公开(公告)号：US08765535B2
公开(公告)日：2014-07-01
申请号：US13278654
申请日：2011-10-21
申请人： Kengo Akimoto
发明人： Kengo Akimoto
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/30 , H01L21/46
CPC分类号： H01L27/1266 , H01L27/1255 , H01L29/04 , H01L29/78654
摘要： In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.
摘要翻译：在本发明的半导体装置的制造方法中，在基板上形成接合层，在接合层上形成绝缘膜和辅助电容部下部电极，在绝缘膜上形成单晶硅层，在保持电容器部分下电极上形成存储电容器部分绝缘膜，在单晶硅层上方形成有在辅助电容部分绝缘膜上的布线，沟道形成区和低浓度杂质区，绝缘膜和栅电极形成在单晶硅层上。存储电容器部分绝缘膜通过沉积具有用作基膜的单晶硅层的YSZ膜形成，从而电容率增加，从而抑制了来自存储电容器部分的漏电流。

48. 发明授权

US08753966B2 Method for fabricating buried gates using pre landing plugs 有权
标题翻译：使用预先着陆插头制造埋地门的方法
公开(公告)号：US08753966B2
公开(公告)日：2014-06-17
申请号：US13745387
申请日：2013-01-18
申请人： SK hynix Inc.
发明人： Jum-Yong Park , Jong-Han Shin
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8242 , H01L29/423 , H01L21/28 , H01L27/108 , H01L27/105
CPC分类号： H01L21/28017 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
摘要翻译：提供一种制造半导体器件的方法，该方法包括在衬底的整个表面上形成插头导电层，蚀刻插头导电层以形成着陆塞，蚀刻层压塞之间的衬底以形成沟槽，形成栅极绝缘层，并且形成在门绝缘层上部分地填充沟槽的掩埋栅极。

49. 发明授权

US08753933B2 Methods for forming a conductive material, methods for selectively forming a conductive material, methods for forming platinum, and methods for forming conductive structures 有权
标题翻译：用于形成导电材料的方法，用于选择性地形成导电材料的方法，用于形成铂的方法，以及用于形成导电结构的方法
公开(公告)号：US08753933B2
公开(公告)日：2014-06-17
申请号：US12274169
申请日：2008-11-19
申请人： Eugene P. Marsh
发明人： Eugene P. Marsh
IPC分类号： H01L21/8242
CPC分类号： H01L21/7687 , C23C16/04 , C23C16/18 , H01L21/2855 , H01L23/5223 , H01L27/10852 , H01L28/65 , H01L28/91 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Methods of selectively forming a conductive material and methods of forming metal conductive structures are disclosed. An organic material may be patterned to expose regions of an underlying material. The underlying material may be exposed to a precursor gas, such as a platinum precursor gas, that reacts with the underlying material without reacting with the remaining portions of the organic material located over the underlying material. The precursor gas may be used in an atomic layer deposition process, during which the precursor gas may selectively react with the underlying material to form a conductive structure, but not react with the organic material. The conductive structures may be used, for example, as a mask for patterning during various stages of semiconductor device fabrication.
摘要翻译：公开了选择性地形成导电材料的方法和形成金属导电结构的方法。有机材料可以被图案化以暴露下面的材料的区域。潜在的材料可能暴露于前体气体，例如铂前体气体，其与下面的材料反应，而不与位于下面的材料上方的有机材料的其余部分反应。前体气体可以用于原子层沉积过程中，在此期间，前体气体可以选择性地与下面的材料反应以形成导电结构，但不与有机材料反应。导电结构可以用作例如在半导体器件制造的各个阶段期间用于图案化的掩模。

50. 发明授权

US08728887B2 Method for fabricating capacitor of semiconductor device 有权
标题翻译：制造半导体器件电容器的方法
公开(公告)号：US08728887B2
公开(公告)日：2014-05-20
申请号：US13468319
申请日：2012-05-10
申请人： Jeong-Yeop Lee , Hyung-Soon Park , Young-Bang Lee , Su-Young Kim
发明人： Jeong-Yeop Lee , Hyung-Soon Park , Young-Bang Lee , Su-Young Kim
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10852
摘要： A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer.
摘要翻译：一种用于制造半导体器件的电容器的方法包括在衬底上顺序地形成蚀刻停止层和模具层，在模具层上依次形成支撑层和硬掩模图案，通过蚀刻支撑体形成存储节点孔层和模具层，使用硬掩模图案作为蚀刻阻挡层，在存储节点孔内部的模具层的侧壁上形成阻挡层，蚀刻存储节点孔下方的蚀刻停止层，在其内部形成存储节点存储节点孔，以及去除硬掩模图案，模具层和阻挡层。

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