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51. 发明授权

US08937488B2 Calibration of impedance 有权
标题翻译：阻抗校准
公开(公告)号：US08937488B2
公开(公告)日：2015-01-20
申请号：US14266217
申请日：2014-04-30
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshiro Riho
IPC分类号： H03K17/16 , H03K19/00
CPC分类号： H03K19/0005 , H03K19/018521 , H04L25/0278
摘要： A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.
摘要翻译：半导体器件具有第一受控芯片，包括具有与第一输出电路相同的配置的第一复制输出电路，连接到第一复制输出电路的第一ZQ端子，连接到第一ZQ端子的第一通电极和第一控制电路，其设置第一复制输出电路的阻抗。控制芯片包括连接到第一贯通电极的第二ZQ端子，将第二ZQ端子的电压与参考电压进行比较的比较器电路，以及基于比较器电路进行比较的处理的第二控制电路123 。第一控制电路和第二控制电路接收公共输入信号以操作并顺序地改变和设置阻抗，直到当外部电阻元件连接到第二ZQ端子时比较结果改变。

52. 发明授权

US08924903B2 Semiconductor device having plural memory chip 有权
标题翻译：具有多个存储芯片的半导体器件
公开(公告)号：US08924903B2
公开(公告)日：2014-12-30
申请号：US13288631
申请日：2011-11-03
申请人： Akira Ide
发明人： Akira Ide
IPC分类号： G06F17/50 , G11C5/04 , H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , G11C5/04 , G11C11/408 , H01L23/481 , H01L23/50 , H01L2224/16145 , H01L2225/06544
摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
摘要翻译：半导体器件包括堆叠的多个存储器芯片。存储器芯片各自包括多个存储体，分配给各个存储体的多个读/写总线和分配给各个读/写总线并经由存储芯片布置的多个贯穿电极。布置在层叠方向上看到的相同位置的穿透电极在芯片之间共同连接。响应于访问请求，存储器芯片激活被布置在层叠方向上的各个不同位置的存储体，由此通过位于不同平面位置的穿透电极同时输入/输出数据。

53. 发明授权

US08917130B2 Semiconductor device including a delay locked loop circuit 有权
标题翻译：半导体器件包括延迟锁定环电路
公开(公告)号：US08917130B2
公开(公告)日：2014-12-23
申请号：US14152488
申请日：2014-01-10
申请人： Ryo Fujimaki
发明人： Ryo Fujimaki
IPC分类号： H03L7/00 , H03L7/10 , H03L7/081
CPC分类号： H03L7/10 , H03L7/0814
摘要： A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.
摘要翻译：用于初始化具有延迟电路的延迟锁定环路的方法包括多个串行连接的延迟元件和用于选择延迟元件之一的输出作为输出时钟信号的计数器电路。该方法包括复位初始延迟控制电路，利用初始延迟控制电路产生基于输入时钟信号的周期的脉冲，利用初始延迟控制电路确定产生延迟所需的延迟元件的数量时间至少基本上等于预设信号的脉冲宽度，基于预置信号初始化计数器电路，并响应于输入和输出时钟信号的相位调整计数器电路。

54. 发明授权

US08901673B2 Semiconductor device having ring-shaped gate electrode, design apparatus, and program 有权
标题翻译：具有环形栅电极的半导体器件，设计装置和程序
公开(公告)号：US08901673B2
公开(公告)日：2014-12-02
申请号：US14029428
申请日：2013-09-17
申请人： PS4 Luxco S.a.r.l.
发明人： Takamitsu Onda
IPC分类号： H01L27/088 , H01L29/78 , H01L29/423 , H01L27/02 , H01L27/105 , H01L27/108 , H03K5/24
CPC分类号： H01L29/78 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L29/4238 , H03K5/2481 , Y10S438/926
摘要： A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
摘要翻译：半导体器件包括：衬底; 在基板上形成有环状栅电极的晶体管; 多个外部虚拟电极，其布置在栅电极的外部并形成在与栅电极相同的层中; 以及至少一个内部虚设电极，其布置在栅极内部并形成在与栅电极相同的层中。

55. 发明授权

US08886893B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08886893B2
公开(公告)日：2014-11-11
申请号：US12597097
申请日：2008-04-25
申请人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Haraguchi , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00 , G11C7/00 , G06F13/42
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的是提供一种高速，低成本和用户友好的信息处理系统，其可以确保存储器容量的可扩展性。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过串行连接信息处理装置，易失性存储器和非易失性存储器并减少连接信号的数量，提高处理速度，同时保持存储容量的可扩展性。当将非易失性存储器的数据传送到易失性存储器时，执行错误校正，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，其中芯片被交替堆叠和布置，并且由球栅阵列（BGA）或芯片之间的接合进行布线。

56. 发明授权

US08885431B2 Semiconductor device changing an active time-out time interval 有权
标题翻译：半导体器件改变主动超时时间间隔
公开(公告)号：US08885431B2
公开(公告)日：2014-11-11
申请号：US13137030
申请日：2011-07-15
申请人： Tomoaki Sato
发明人： Tomoaki Sato
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/40622
摘要： A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas to produce a determined number, a second control circuit controlling, in accordance with the one refresh requirement signal at a time, refresh operation with respect to the refresh-target memory areas, and a third control circuit adjusting, in connection with the refresh operation, an active time-out time interval according to the determined number. The active time-out time interval indicates a time interval from a first time instant when the sense amplifiers are activated to a second time instant when word lines related to the refresh-target memory areas are inactivated.
摘要翻译：一种设备包括多个存储区域，每个存储区域包括执行由多个读出放大器存储的信息的刷新所需的多个存储器单元;第一控制电路一次确定与一次刷新需求信号相关的数量刷新目标存储器区域以产生确定的数量，第二控制电路根据一次刷新需求信号一次控制相对于刷新目标存储区域的刷新操作，以及第三控制电路，在连接中调整随着刷新操作，根据确定的数量，有效的超时时间间隔。激活超时时间间隔表示当从与刷新目标存储器区域相关的字线被激活时，将感测放大器激活的第一时刻到第二时刻的时间间隔。

57. 发明授权

US08878070B2 Wiring board and method of manufacturing a semiconductor device 有权
标题翻译：接线板及制造半导体器件的方法
公开(公告)号：US08878070B2
公开(公告)日：2014-11-04
申请号：US13222542
申请日：2011-08-31
申请人： Emi Kashiwaya , Osamu Kindo , Noriou Shimada
发明人： Emi Kashiwaya , Osamu Kindo , Noriou Shimada
IPC分类号： H05K1/00 , H01L23/31 , H01L21/56 , H05K3/00 , H05K3/28 , H01L23/00 , H05K1/02 , H05K3/40 , H01L23/498
CPC分类号： H05K3/284 , H01L21/561 , H01L21/565 , H01L23/3142 , H01L23/49838 , H01L24/48 , H01L24/97 , H01L2223/58 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H05K1/0271 , H05K3/0097 , H05K3/4015 , H05K2203/041 , H05K2203/1316 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.
摘要翻译：本发明的布线基板包括产品形成区域，在该产品形成区域中布置有安装有半导体芯片的多个产品形成部分; 成形区域，其设置在所述产品形成区域的外周侧，并且覆盖安装在所述产品形成部分上的所述半导体芯片的密封部分与所述成型区域接触; 夹紧区域，设置在成型区域的外周侧，并且由形成密封部的成型模具保持; 设置在产品形成区域中并与半导体芯片电连接的布线; 第一固体图案，其设置在成型区域中，并且其中布置有多个点; 以及设置在所述夹持区域中的第二固体图案，并且其中布置有大于所述第一固体图案的点的多个点。

58. 发明授权

US08872560B2 Semiconductor device having data output circuit in which slew rate thereof is adjustable 有权
标题翻译：具有其压摆率可调的数据输出电路的半导体装置
公开(公告)号：US08872560B2
公开(公告)日：2014-10-28
申请号：US13710626
申请日：2012-12-11
申请人： Elpida Memory, Inc.
发明人： Yoshihito Morishita , Tetsuya Arai
IPC分类号： H03K5/12 , H03K3/00 , H03K19/003
CPC分类号： H03K5/12 , H03K3/00 , H03K19/00361
摘要： Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals.
摘要翻译：这里公开了一种装置，其包括：第一电路，被配置为在第一电源电压上操作以产生第一组转换速率控制信号; 第二电路，被配置为响应于所述第一组转换速率控制信号而在第二电源电压上操作以产生第二组转换速率控制信号; 以及第三电路，被配置为对所述第二电源电压进行操作，以响应于所述第二组压摆率控制信号可控制的速率产生信号。

59. 发明授权

US08872258B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08872258B2
公开(公告)日：2014-10-28
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.
摘要翻译：半导体存储器件包括：读出放大器; 多个存储单元阵列; 共享MOS晶体管，其连接/断开读出放大器和存储单元阵列中包含的位线; 以及控制所述共享MOS晶体管的动作的控制电路。作为连接读出放大器和共享MOS晶体管的位线的读出放大器位线的一部分或全部嵌入在半导体衬底中。

60. 发明授权

US08860476B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
公开(公告)号：US08860476B2
公开(公告)日：2014-10-14
申请号：US14158253
申请日：2014-01-17
申请人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03L7/081 , H03K5/159 , H03K5/13 , H03K5/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

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