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51. 发明授权

US07099773B2 Navigation system allowing to remove selected items from route for recalculating new route to destination 有权
标题翻译：导航系统允许从路线中删除所选项目，以重新计算新路线到目的地
公开(公告)号：US07099773B2
公开(公告)日：2006-08-29
申请号：US10704397
申请日：2003-11-06
申请人： Jian-Liang Linn
发明人： Jian-Liang Linn
IPC分类号： G01C21/30
CPC分类号： G01C21/28 , G01C21/3415 , G01C21/3461 , G01C21/3484 , G01C21/3492 , G01C21/3682
摘要： A method for navigation system modifies a route to the destination by allowing a user to select a type of items or conditions to be avoided from the route. The method includes the steps of displaying a set of data indicating items that a user will encounter when the user follows the calculated route, prompting the user to select a type of the item to be avoided in a new route to the destination, and recalculating the new route according to the user's selection and guiding the user to the destination through the new route. The navigation system displays the set of items which is classified into distance ranges each representing a range of distance from a current user position where each item is represented by a corresponding icon.
摘要翻译：导航系统的方法通过允许用户从路线中选择要避免的项目或条件的类型来修改到目的地的路线。该方法包括以下步骤：当用户遵循计算出的路线时，显示用户将遇到的项目的一组数据，提示用户在到目的地的新路线中选择要避免的项目的类型，并重新计算根据用户选择的新路由，并通过新路由将用户引导到目的地。导航系统显示被分类为距离范围的项目组，每个距离范围表示与当前用户位置的距离的距离，其中每个项目由相应的图标表示。

52. 发明授权

US07089517B2 Method for design validation of complex IC 失效
标题翻译：复杂IC设计验证方法
公开(公告)号：US07089517B2
公开(公告)日：2006-08-08
申请号：US09941396
申请日：2001-08-28
申请人： Hiroaki Yamoto , Rochit Rajsuman
发明人： Hiroaki Yamoto , Rochit Rajsuman
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F11/261 , G06F17/5022
摘要： A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
摘要翻译：利用电子设计自动化（EDA）工具和设计测试站的组合，以高速，低成本的方式对复杂IC进行设计验证。 EDA工具和设备模拟器链接到基于事件的测试系统，以执行原始设计模拟向量和测试平台，并在测试平台和基于事件的测试向量中进行修改，直到获得满意的结果。基于事件的测试向量是事件格式中的测试向量，其中事件是由其定时描述的信号中的任何变化，并且基于事件的测试系统是通过利用基于事件的测试向量来测试IC的测试系统。由于EDA工具与基于事件的测试系统相关联，因此捕获这些修改以生成最终的测试平台，从而提供令人满意的结果。

53. 发明授权

US07078889B2 Semiconductor test apparatus for testing semiconductor device that produces output data by its internal clock timing 失效
标题翻译：用于测试通过其内部时钟时序产生输出数据的半导体器件的半导体测试装置
公开(公告)号：US07078889B2
公开(公告)日：2006-07-18
申请号：US10507042
申请日：2003-12-26
申请人： Hideyuki Oshima
发明人： Hideyuki Oshima
IPC分类号： G01R31/26
CPC分类号： G01R31/31922
摘要： A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention includes: a time interpolator 20 which includes flip-flops (FF 21) which receive system clocks of the DUT 1, a delay circuit 22 which outputs time-series level data, from the FF 21, and an encoder 28 which receives the time-series level data output and encodes it into positional data indicative of an edge timing; a digital filter 40 which includes a plurality of registers 41 which sequentially store the positional data and output the positional data as a recovery clock; and a data side selector 30 which selects output data of the DUT 1 base on the recovery clock.
摘要翻译：在系统时钟从DUT的输出的边沿定时获得与系统时钟相比内部时钟同步的恢复时钟。本发明包括：时间插补器20，其包括接收DUT1的系统时钟的触发器（FF21），从FF21输出时间序列电平数据的延迟电路22和接收时间序列电平数据输出并将其编码成表示边缘定时的位置数据; 数字滤波器40，其包括多个寄存器41，其顺序地存储位置数据并输出位置数据作为恢复时钟; 以及数据侧选择器30，其基于恢复时钟选择DUT 1的输出数据。

54. 发明授权

US07041988B2 Electron beam exposure apparatus and electron beam processing apparatus 失效
标题翻译：电子束曝光装置和电子束处理装置
公开(公告)号：US07041988B2
公开(公告)日：2006-05-09
申请号：US10431782
申请日：2003-05-08
申请人： Shinichi Hamaguchi , Susumu Goto , Osamu Kamimura , Yasunari Sohda
发明人： Shinichi Hamaguchi , Susumu Goto , Osamu Kamimura , Yasunari Sohda
IPC分类号： G21G5/00 , G21K5/10
CPC分类号： B82Y10/00 , B82Y40/00 , G21K1/093 , H01J37/153 , H01J37/3177 , H01J2237/1536
摘要： An electron beam exposure apparatus for exposing wafer with an electron beam, includes: a first electromagnetic lens system for making the electron beam incident substantially perpendicularly on a first plane be incident on a second plane substantially perpendicularly; a second electromagnetic lens system for making the electron beam that was substantially perpendicularly incident on the second plane be incident on the wafer substantially perpendicularly; a rotation correction lens provided within the first electromagnetic lens system for correcting rotation of the electron beam caused by at least the first electromagnetic lens system; a deflection system for deflecting the electron beam to a position on the wafer; and a deflection-correction optical system provided within the second electromagnetic lens system for correcting deflection aberration caused by the deflection system.
摘要翻译：一种用电子束曝光晶片的电子束曝光装置，包括：用于使基本上垂直于第一平面的电子束入射到第二平面上的第一电磁透镜系统基本垂直入射; 用于使基本上垂直入射在第二平面上的电子束的第二电磁透镜系统基本上垂直入射在晶片上; 旋转校正透镜，设置在第一电磁透镜系统内，用于校正由至少第一电磁透镜系统引起的电子束的旋转; 用于将电子束偏转到晶片上的位置的偏转系统; 以及设置在第二电磁透镜系统内用于校正由偏转系统引起的偏转像差的偏转校正光学系统。

55. 发明授权

US07034518B2 Timing generator and semiconductor test apparatus 失效
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US07034518B2
公开(公告)日：2006-04-25
申请号：US10484980
申请日：2002-07-26
申请人： Kazuhiro Yamamoto
发明人： Kazuhiro Yamamoto
IPC分类号： G01R31/26
CPC分类号： G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00071 , H03K2005/00084
摘要： There is provided a timing generator capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum. The timing generator is configured to include a selection unit which assigns five-bit delay device candidates to a three-bit partial bit signal of all the bit signals constituting the path data outputted from a linearization memory and selects three delay devices whose number is equal to the bit count of the partial bit signal.
摘要翻译：提供一种能够吸收可变延迟电路的延迟时间误差的定时发生器，而不增加路径数据的位数，并将定时精度的降低从设计值降低到最小。定时发生器被配置为包括一个选择单元，该选择单元将构成从线性化存储器输出的路径数据的所有比特信号的3比特部分比特信号分配给5比特延迟装置候选，并且选择三个等于部分位信号的位计数。

56. 发明授权

US07034321B2 Electron beam exposure apparatus and electron beam measurement module 失效
标题翻译：电子束曝光装置和电子束测量模块
公开(公告)号：US07034321B2
公开(公告)日：2006-04-25
申请号：US10624423
申请日：2003-07-21
申请人： Masaki Takakuwa , Yoshinori Nakayama , Gen Nakamura
发明人： Masaki Takakuwa , Yoshinori Nakayama , Gen Nakamura
IPC分类号： H01J37/304 , H01J37/244 , G01R29/24
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/304 , H01J37/3174
摘要： An electron beam exposure apparatus for exposing wafer by using an electron beam includes: an electron beam generator for generating the electron beam; a wafer stage for holding the wafer to be exposed; a current detector, provided on the wafer stage, for detecting a current of the electron beam; and a storage unit, provided on the wafer stage, for storing information indicating the current detected by the current detector.
摘要翻译：用于通过使用电子束曝光晶片的电子束曝光装置包括：用于产生电子束的电子束发生器; 用于保持要暴露的晶片的晶片台; 设置在晶片台上的电流检测器，用于检测电子束的电流; 以及设置在晶片台上的用于存储指示由电流检测器检测到的电流的信息的存储单元。

57. 发明授权

US07019848B2 Three-dimensional measuring instrument, filter striped plate, and illuminating means 有权
标题翻译：三维测量仪器，过滤条纹板和照明装置
公开(公告)号：US07019848B2
公开(公告)日：2006-03-28
申请号：US10503150
申请日：2003-01-20
申请人： Takahiro Mamiya
发明人： Takahiro Mamiya
IPC分类号： G01B11/24 , G01V8/00 , G06K9/00
CPC分类号： G01B11/245 , G01B11/24 , G01B11/25 , H05K3/3484
摘要： For measuring the three-dimensional shape of an object of measurement using a phase shift method, a three-dimensional measuring instrument is provided which is capable of shortening the measurement time. A printed state inspection device 1 includes a table for placing a printed circuit board K printed with cream solder H, an illumination device 3 for illuminating three sine wave light component patterns with different phases on the surface of printed circuit board K, a CCD camera 4 for picking-up images of the illuminated part of the printed circuit board K, a white light illumination unit L for illuminating a white light on the surface of printed circuit board K, and a laser pointer for measuring the standard height. A control device 7 determines the existing area of the cream solder H from the image data obtained by the illumination of the white light, and calculates the height of the cream solder H from the image data obtained by the illumination device 3 by using a phase shift method.
摘要翻译：为了使用相移法测量测量对象的三维形状，提供了能够缩短测量时间的三维测量仪器。印刷状态检查装置1包括用于放置印刷有膏状焊料H的印刷电路板K的台，用于在印刷电路板K的表面上照射具有不同相位的三个正弦波光成分图案的照明装置3，CCD照相机4 用于拍摄印刷电路板K的照明部分的图像，用于照射印刷电路板K的表面上的白光的白光照明单元L和用于测量标准高度的激光指示器。控制装置7根据通过照明白光获得的图像数据来确定膏状焊料H的现有面积，并且通过使用相移来计算由照明装置3获得的图像数据中的膏状焊料H的高度方法。

58. 发明授权

US06934705B2 Data sorting method and navigation method and system using the sorting method 有权
标题翻译：数据排序方法和导航方法及系统采用排序方法
公开(公告)号：US06934705B2
公开(公告)日：2005-08-23
申请号：US10217250
申请日：2002-08-12
申请人： Ihung S. Tu
发明人： Ihung S. Tu
IPC分类号： G01C21/00 , G06F7/00 , G06F7/22 , G06F7/24 , G06F17/30
CPC分类号： G06F7/22 , Y10S707/99937 , Y10S707/99945
摘要： A computer-implemented data sorting method for sorting data at high speed with small memory capacity. The sorting method sorts an array of data where sorted data is constituted by a combination of a plurality of blocks where each block is produced separately from one another during the sorting process. In another aspect, a navigation method and system utilizes the data sorting method for quickly sorting and displaying requested information such as POIs sorted by distance with use of a small memory.
摘要翻译：一种计算机实现的数据排序方法，用于以较小的存储容量高速分类数据。排序方法对排序数据由排序处理中的每个块彼此分离地生成的多个块的组合构成的数据排序。在另一方面，导航方法和系统利用数据排序方法快速排序和显示使用小存储器按距离分类的POI等请求信息。

59. 发明授权

US06916520B2 Set for laminating a print carrier element with a protective film element 失效
标题翻译：用于层压具有保护膜元件的印刷载体元件
公开(公告)号：US06916520B2
公开(公告)日：2005-07-12
申请号：US10385776
申请日：2003-03-11
申请人： Paul Fernandez-Kirchberger
发明人： Paul Fernandez-Kirchberger
IPC分类号： B32B7/06 , B32B27/06 , B42D25/00 , B32B3/14
CPC分类号： B42D25/455 , B32B7/06 , B32B27/06 , B42D25/00 , B42D25/23 , B42D25/46 , Y10T428/14 , Y10T428/1486 , Y10T428/22 , Y10T428/24967 , Y10T428/31544
摘要： A set for forming a card such as an identity card with a protective film. The set has a carrier sheet, a print carrier layer and a protective film layer. The set further includes at least one print carrier element stamped out from the print carrier layer, and at least one protective film element stamped out from the protective film layer. The print carrier element and the protective film element are disposed in a mirror image relative to a fold axis formed in the carrier sheet. The protective film layer is formed by a hot-seal film layer, and the protective film element is disposed on the carrier sheet with a horizontal gap having a predetermined distance from the adjoining regions of the hot-seal film layer.
摘要翻译：用于形成诸如具有保护膜的身份证的卡的套件。该组具有载体片，印刷载体层和保护膜层。该组件还包括从印刷载体层冲压出的至少一个印刷载体元件和从保护膜层冲压出的至少一个保护膜元件。印刷载体元件和保护膜元件相对于形成在载体片材中的折叠轴线设置成镜像。保护膜层由热封膜层形成，保护膜元件以与热封膜层的相邻区域相隔一定距离的水平间隙配置在载体片上。

60. 外观设计

USD506116S1 Portion of scissors 失效
标题翻译：剪刀部分
公开(公告)号：USD506116S1
公开(公告)日：2005-06-14
申请号：US29206617
申请日：2004-06-01
申请人： Hidemi Adachi
设计人： Hidemi Adachi

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