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51. 发明申请

US20080100628A1 Single Precision Vector Permute Immediate with "Word" Vector Write Mask 审中-公开
标题翻译：单精度向量允许立即与“Word”向量写入掩码
公开(公告)号：US20080100628A1
公开(公告)日：2008-05-01
申请号：US11925217
申请日：2007-10-26
申请人： Eric Oliver Mejdrich , Adam James Muff
发明人： Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F15/16
CPC分类号： G06T1/60
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a cross product. The permute instructions may be dependent on one another and may require the use of temporary registers. Embodiments of the invention provide a permute instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby reducing the number of instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.
摘要翻译：本发明通常涉及集成电路装置，更具体地涉及图像处理领域的方法，系统和设计结构，更具体地涉及用于处理图像的指令集。矢量处理可以包括执行多个置换操作，以在执行矢量操作之前（例如，交叉乘积）将向量操作数布置在寄存器的期望位置中。置换指令可能彼此依赖，可能需要使用临时寄存器。本发明的实施例提供了一种置换指令，其中掩模字段可以用于指定目标寄存器的特定位置，其中传送数据，从而减少用于排列数据的指令的数量，减少指令之间的依赖性以及临时的使用注册

52. 发明申请

US20080079712A1 Dual Independent and Shared Resource Vector Execution Units With Shared Register File 审中-公开
标题翻译：具有共享寄存器文件的双独立和共享资源向量执行单元
公开(公告)号：US20080079712A1
公开(公告)日：2008-04-03
申请号：US11536146
申请日：2006-09-28
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F15/8092 , G06T15/005
摘要： The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于支持图像处理的矢量单元。描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。向量单元可以独立地并且同时处理指令。此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

53. 发明申请

US20150379376A1 SYSTEM AND METHOD FOR CLASSIFYING PIXELS 有权
标题翻译：用于分类像素的系统和方法
公开(公告)号：US20150379376A1
公开(公告)日：2015-12-31
申请号：US14318135
申请日：2014-06-27
申请人： Adam James Muff , John Allen Tardif , Susan Carrie , Mark J. Finocchio , Kyungsuk David Lee , Christopher Douglas Edmonds , Randy Crane
发明人： Adam James Muff , John Allen Tardif , Susan Carrie , Mark J. Finocchio , Kyungsuk David Lee , Christopher Douglas Edmonds , Randy Crane
IPC分类号： G06K9/62
CPC分类号： G06K9/6267 , G06K9/00973 , G06K9/6282
摘要： Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.
摘要翻译：公开了涉及处理图像像素的实施例。例如，一个公开的实施例提供了一种用于对包括检索逻辑的像素进行分类的系统; 包括多个像素时隙的像素存储分配，每个像素时隙与像素相关联，其中所述检索逻辑被配置为使所述像素被分配到输入序列中的所述像素时隙中; 流水线处理逻辑被配置为针对每个像素输出与像素相关联的分类信息; 以及调度逻辑，被配置为控制从像素时隙到流水线处理逻辑的调度，其中调度逻辑和流水线处理逻辑被配置为一致地起作用以产生与输出序列不同且独立于的输出序列中的像素的分类信息输入序列。

54. 发明申请

US20120303691A1 EXECUTION UNIT WITH INLINE PSEUDORANDOM NUMBER GENERATOR 审中-公开
标题翻译：具有内置PSEUDORANDOM数字发生器的执行单元
公开(公告)号：US20120303691A1
公开(公告)日：2012-11-29
申请号：US13556464
申请日：2012-07-24
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/58
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/30181
摘要： A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.
摘要翻译：电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数，执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。

55. 发明授权

US08310497B2 Anisotropic texture filtering with texture data prefetching 有权
公开(公告)号：US08310497B2
公开(公告)日：2012-11-13
申请号：US13421169
申请日：2012-03-15
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.

56. 发明授权

US08275821B2 Area efficient transcendental estimate algorithm 失效
标题翻译：区域有效超验估计算法
公开(公告)号：US08275821B2
公开(公告)日：2012-09-25
申请号：US11851658
申请日：2007-09-07
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/38 , G06F1/02
CPC分类号： G06F7/548
摘要： A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.
摘要翻译：一种用于产生超验值的方法，计算机可读介质和装置。该方法包括接收包含输入值和操作码的输入，并确定操作码是否对应于三角运算或二进制运算。该方法还包括从输入值计算分数值和整数值，通过将分数值的至少一部分与通过移动部分产生的移位分数值中的至少一个相加而基于分数值生成超越值的分数值和恒定值，并且响应于该请求提供超验值。以这种方式，可以使用相同的电路面积来执行三角和二次幂计算，导致更大的电路面积节省和性能优点，而不牺牲显着的精度。

57. 发明授权

US08082420B2 Method and apparatus for executing instructions 有权
标题翻译：用于执行指令的方法和装置
公开(公告)号：US08082420B2
公开(公告)日：2011-12-20
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译：提供了一种用于在处理器中执行指令的方法和装置。在本发明的一个实施例中，该方法包括接收多个指令。多个指令包括第一线程中的第一指令和第二线程中的第二指令。该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。该方法还包括向第一执行单元和第二执行单元发布公共问题组。向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。

58. 发明授权

US07941644B2 Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer 失效
标题翻译：同时多线程指令发送到执行单元，同时通过多路复用器代替长延迟定序器指令的指令序列
公开(公告)号：US07941644B2
公开(公告)日：2011-05-10
申请号：US12252541
申请日：2008-10-16
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/46
CPC分类号： G06F9/3885 , G06F9/22 , G06F9/3009 , G06F9/3851 , G06F9/3867
摘要： A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation.
摘要翻译：处理单元包括多个执行单元和定序器逻辑，其布置在指令缓冲器逻辑的下游，并且响应于指令流中存在的定序器指令。响应于这样的指令，定序器逻辑向一个执行单元发出与长等待时间操作相关联的多个指令，同时阻止来自指令缓冲器逻辑的指令被发布到该执行单元。此外，指令的阻塞被发布到执行单元不影响向任何其他执行单元发出指令，因此来自指令缓冲器逻辑的其他指令仍然能够被发出并由其他执行执行即使当定序器逻辑发出与长延迟操作相关联的多个指令时。

59. 发明授权

US07904700B2 Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control 失效
标题翻译：包含专用寄存器的处理单元，用于基于指令的持久矢量多路复用器控制
公开(公告)号：US07904700B2
公开(公告)日：2011-03-08
申请号：US12045222
申请日：2008-03-10
申请人： Eric Oliver Mejdrich , Adam James Muff , Robert Allen Shearer , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Robert Allen Shearer , Matthew Ray Tubbs
IPC分类号： G06F9/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30123
摘要： A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be stored in the special purpose register such that the operand vectors processed by subsequent vector instructions executed by the vector-based execution unit will be selectively shuffled using the persisted state information. As a result, when multiple vector instructions require a common custom word ordering for one or more operand vectors, a single persistent swizzle instruction may be used to select the desired custom word ordering for all of the vector instructions.
摘要翻译：软件可访问专用寄存器被设计成处理单元，以便实现基于向量的执行单元的持久矢量多路复用器控制。在基于向量的执行单元的指令集中定义持续转换指令，并且用于使状态信息存储在专用寄存器中，使得由基于向量的执行单元执行的后续向量指令处理的操作数向量将使用持久状态信息选择性地进行混洗。因此，当多个向量指令需要一个或多个操作数向量的公共自定义单词排序时，可以使用单个持续旋转指令来选择所有向量指令的期望的定制单词排序。

60. 发明申请

US20090315908A1 Anisotropic Texture Filtering with Texture Data Prefetching 有权
标题翻译：各向异性纹理过滤与纹理数据预取
公开(公告)号：US20090315908A1
公开(公告)日：2009-12-24
申请号：US12110045
申请日：2008-04-25
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00 , G06K9/40
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

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