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1. 发明申请

US20090113181A1 Method and Apparatus for Executing Instructions 有权
标题翻译：执行指令的方法和装置
公开(公告)号：US20090113181A1
公开(公告)日：2009-04-30
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译：提供了一种用于在处理器中执行指令的方法和装置。在本发明的一个实施例中，该方法包括接收多个指令。多个指令包括第一线程中的第一指令和第二线程中的第二指令。该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。该方法还包括向第一执行单元和第二执行单元发布公共问题组。向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。

2. 发明授权

US08082420B2 Method and apparatus for executing instructions 有权
标题翻译：用于执行指令的方法和装置
公开(公告)号：US08082420B2
公开(公告)日：2011-12-20
申请号：US11877754
申请日：2007-10-24
申请人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
发明人： Miguel Comparan , Brent Francis Hilgart , Brian Lee Koehler , Eric Oliver Mejdrich , Adam James Muff , Alfred Thomas Watson, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
摘要翻译：提供了一种用于在处理器中执行指令的方法和装置。在本发明的一个实施例中，该方法包括接收多个指令。多个指令包括第一线程中的第一指令和第二线程中的第二指令。该方法还包括形成包括第一指令类型的指令和第二指令类型的指令的公共发行组。该方法还包括向第一执行单元和第二执行单元发布公共问题组。向第一执行单元发出第一指令类型的指令，并向第二执行单元发出第二指令类型的指令。

3. 发明授权

US08217953B2 Anisotropic texture filtering with texture data prefetching 有权
标题翻译：具有纹理数据预取的各向异性纹理过滤
公开(公告)号：US08217953B2
公开(公告)日：2012-07-10
申请号：US12110045
申请日：2008-04-25
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

4. 发明授权

US07890699B2 Processing unit incorporating L1 cache bypass 失效
标题翻译：包含L1缓存旁路的处理单元
公开(公告)号：US07890699B2
公开(公告)日：2011-02-15
申请号：US11972221
申请日：2008-01-10
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译：在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性缓存。然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。

5. 发明申请

US20120169755A1 ANISOTROPIC TEXTURE FILTERING WITH TEXTURE DATA PREFETCHING 有权
标题翻译：具有纹理数据预选的各向异性纹理滤波
公开(公告)号：US20120169755A1
公开(公告)日：2012-07-05
申请号：US13421169
申请日：2012-03-15
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

6. 发明授权

US08310497B2 Anisotropic texture filtering with texture data prefetching 有权
公开(公告)号：US08310497B2
公开(公告)日：2012-11-13
申请号：US13421169
申请日：2012-03-15
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.

7. 发明申请

US20090315908A1 Anisotropic Texture Filtering with Texture Data Prefetching 有权
标题翻译：各向异性纹理过滤与纹理数据预取
公开(公告)号：US20090315908A1
公开(公告)日：2009-12-24
申请号：US12110045
申请日：2008-04-25
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00 , G06K9/40
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

8. 发明申请

US20090182944A1 Processing Unit Incorporating L1 Cache Bypass 失效
标题翻译：结合L1缓存旁路的处理单元
公开(公告)号：US20090182944A1
公开(公告)日：2009-07-16
申请号：US11972221
申请日：2008-01-10
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译：在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性缓存。然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。

9. 发明申请

US20090070398A1 Method and Apparatus for an Area Efficient Transcendental Estimate Algorithm 失效
标题翻译：用于区域有效超验估计算法的方法和装置
公开(公告)号：US20090070398A1
公开(公告)日：2009-03-12
申请号：US11851658
申请日：2007-09-07
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/38
CPC分类号： G06F7/548
摘要： A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.
摘要翻译：一种用于产生超验值的方法，计算机可读介质和装置。该方法包括接收包含输入值和操作码的输入，并确定操作码是否对应于三角运算或二进制运算。该方法还包括从输入值计算分数值和整数值，通过将分数值的至少一部分与通过移动部分产生的移位分数值中的至少一个相加而基于分数值生成超越值的分数值和恒定值，并且响应于该请求提供超验值。以这种方式，可以使用相同的电路面积来执行三角和二次幂计算，导致更大的电路面积节省和性能优点，而不牺牲显着的精度。

10. 发明申请

US20090037694A1 Load Misaligned Vector with Permute and Mask Insert 失效
标题翻译：加载不对齐矢量与Permute和Mask插入
公开(公告)号：US20090037694A1
公开(公告)日：2009-02-05
申请号：US11830920
申请日：2007-07-31
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3816 , G06F9/3824
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

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