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1. 发明申请

US20160180493A1 LOW POWER DMA LABELING 有权
标题翻译：低功率DMA标签
公开(公告)号：US20160180493A1
公开(公告)日：2016-06-23
申请号：US14574093
申请日：2014-12-17
申请人： Ryan Scott Haraden , Matthew Ray Tubbs , Adam James Muff , Robert Allen Shearer
发明人： Ryan Scott Haraden , Matthew Ray Tubbs , Adam James Muff , Robert Allen Shearer
IPC分类号： G06T1/60 , H04N13/00
CPC分类号： G06T1/60 , G06T1/20 , G06T2200/28 , H04N13/139
摘要： Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., a local cache) are described. The pixel data may derive from an image capturing device (e.g., a color camera or a depth camera) in which individual pixel values are not a multiple of eight bits. In some embodiments, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one example, the DMA engine may be configured to identify and label one or more pixels as being within a particular range of pixel values and/or the DMA engine may be configured to label pixels as belonging to one or more pixel groups based on their pixel values.
摘要翻译：描述了在将像素数据从第一存储器（例如，DRAM）到第二存储器（例如，本地高速缓存）的数据传输期间使用直接存储器访问（DMA）引擎预处理像素数据的方法。像素数据可以从其中各个像素值不是8位的倍数的图像捕获设备（例如，彩色照相机或深度相机）导出。在一些实施例中，DMA引擎可以在将像素数据写入第二存储器之前对像素数据执行各种图像处理操作。在一个示例中，DMA引擎可以被配置为将一个或多个像素识别并标记为在像素值的特定范围内，和/或DMA引擎可以被配置为基于它们的像素组将像素标记为属于一个或多个像素组像素值。

2. 发明授权

US09021004B2 Execution unit with inline pseudorandom number generator 有权
标题翻译：具有内联伪随机数发生器的执行单元
公开(公告)号：US09021004B2
公开(公告)日：2015-04-28
申请号：US13556464
申请日：2012-07-24
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/48 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/30181
摘要： A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.
摘要翻译：电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数，执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。

3. 发明授权

US08443027B2 Implementing a floating point weighted average function 有权
标题翻译：实现浮点加权平均函数
公开(公告)号：US08443027B2
公开(公告)日：2013-05-14
申请号：US11861518
申请日：2007-09-26
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/38
CPC分类号： G06F7/483
摘要： A method, computer-readable medium, and an apparatus for implementing a floating point weighted average function. The method includes receiving an input containing 2N input values, 2N weights, and an opcode, where N is a positive integer number and each of the input values corresponds to one of the weights. Furthermore, the method also includes using existing dot product circuit function to generate 2N addends by multiplying each of the input values with the corresponding weight. In addition, the method includes generating a sum value by adding the 2N addends, where the sum value includes an exponent value, and generating the weighted average value based on the sum value by decreasing the exponent value by N. In this fashion, the same circuit area may be used to carry out both dot product and weighted average calculations, leading to greater circuit area savings and performance advantages.
摘要翻译：一种用于实现浮点加权平均函数的方法，计算机可读介质和装置。该方法包括接收包含2N个输入值，2N个权重和操作码的输入，其中N是正整数，并且每个输入值对应于其中一个权重。此外，该方法还包括使用现有的点积电路函数，通过将每个输入值与相应的权重相乘来产生2N个加数。此外，该方法包括通过加上2N加数来产生和值，其中和值包括指数值，并且通过将指数值减小N来基于和值生成加权平均值。以这种方式，相同电路面积可用于进行点积和加权平均计算，从而实现更大的电路面积节省和性能优势。

4. 发明授权

US08356162B2 Execution unit with data dependent conditional write instructions 有权
标题翻译：具有数据相关条件写入指令的执行单元
公开(公告)号：US08356162B2
公开(公告)日：2013-01-15
申请号：US12050721
申请日：2008-03-18
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30072 , G06F9/30043 , G06F9/3851 , G06F9/3885
摘要： An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.
摘要翻译：执行单元支持仅当满足特定条件时将数据写入目标的数据相关条件写指令。在一个实现中，依赖于数据的条件写入指令识别条件以及针对该条件进行测试的数据。根据该条件测试数据，并且测试结果用于选择性地启用或禁用对与数据相关条件写指令相关联的目标的写入。然后，当对目标的写入被启用或禁用时，尝试写入，以便只有当作为测试的结果有选择地启用写入时，写入才会更新目标的内容。通过这样做，通常可以避免依赖关系，因为使用可能会导致分支预测错误处理的架构条件寄存器，可以通过z缓冲区测试和类似类型的算法实现改进的性能。

5. 发明授权

US08255443B2 Execution unit with inline pseudorandom number generator 失效
标题翻译：具有内联伪随机数发生器的执行单元
公开(公告)号：US08255443B2
公开(公告)日：2012-08-28
申请号：US12132115
申请日：2008-06-03
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/58
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/30181
摘要： A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG. In many instances, an instruction executed by an execution unit may be able to perform an arithmetic operation using both an operand specified by the instruction and a pseudorandom number generated by the PRNG during the execution of the instruction, so that the generation of the pseudorandom number and the performance of the arithmetic operation occur during a single pass of an execution unit.
摘要翻译：电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数，执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。在许多情况下，执行单元执行的指令可以在执行指令期间使用由指令指定的操作数和由PRNG生成的伪随机数来执行算术运算，从而生成伪随机数并且算术运算的执行在执行单元的单次通过期间发生。

6. 发明授权

US07814299B2 Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread 失效
标题翻译：通过索引到每个线程的目标寄存器历史记录表来指定指令代码中较少位的操作数
公开(公告)号：US07814299B2
公开(公告)日：2010-10-12
申请号：US12274560
申请日：2008-11-20
申请人： Mark Joseph Hickey , Adam James Muff , Matthew Ray Tubbs , Charles David Wait
发明人： Mark Joseph Hickey , Adam James Muff , Matthew Ray Tubbs , Charles David Wait
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/3832
摘要： A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.
摘要翻译：一种电路布置和方法支持指令目标历史的寄存器地址索引，由此由指令使用的寄存器地址使用先前目标寄存器地址的目标历史表和由目标历史表中的索引值提供的索引进行解码指示。指令可以包括标识先前使用的寄存器地址的至少一个索引值。在执行指令期间，从指令中检索索引，然后使用索引从目标历史表中检索一个寄存器地址。

7. 发明申请

US20100031009A1 Floating Point Execution Unit for Calculating a One Minus Dot Product Value in a Single Pass 失效
标题翻译：浮点执行单元，用于计算单次通过中的一个减号点产品值
公开(公告)号：US20100031009A1
公开(公告)日：2010-02-04
申请号：US12184324
申请日：2008-08-01
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/3802 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06T15/50 , G06T2200/28
摘要： A floating point execution unit calculates a one minus dot product value in a single pass. As such, the dependency that otherwise would be required to perform the calculations is eliminated, resulting in a substantially faster performance of such calculations. The floating point execution unit may be used, for example, to accelerate pixel shading algorithms such as Fresnel and electron microscope effects.
摘要翻译：浮点执行单元在单程中计算一个减去点积积值。因此，消除了否则将执行计算所需的相关性，导致这种计算的性能显着更快。例如，浮点执行单元可以用于加速诸如菲涅耳和电子显微镜效应的像素着色算法。

8. 发明申请

US20090070398A1 Method and Apparatus for an Area Efficient Transcendental Estimate Algorithm 失效
标题翻译：用于区域有效超验估计算法的方法和装置
公开(公告)号：US20090070398A1
公开(公告)日：2009-03-12
申请号：US11851658
申请日：2007-09-07
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F7/38
CPC分类号： G06F7/548
摘要： A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.
摘要翻译：一种用于产生超验值的方法，计算机可读介质和装置。该方法包括接收包含输入值和操作码的输入，并确定操作码是否对应于三角运算或二进制运算。该方法还包括从输入值计算分数值和整数值，通过将分数值的至少一部分与通过移动部分产生的移位分数值中的至少一个相加而基于分数值生成超越值的分数值和恒定值，并且响应于该请求提供超验值。以这种方式，可以使用相同的电路面积来执行三角和二次幂计算，导致更大的电路面积节省和性能优点，而不牺牲显着的精度。

9. 发明申请

US20090037694A1 Load Misaligned Vector with Permute and Mask Insert 失效
标题翻译：加载不对齐矢量与Permute和Mask插入
公开(公告)号：US20090037694A1
公开(公告)日：2009-02-05
申请号：US11830920
申请日：2007-07-31
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3816 , G06F9/3824
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

10. 发明申请

US20080122854A1 Operand Multiplexor Control Modifier Instruction in a Fine Grain Multithreaded Vector Microprocessor 失效
标题翻译：精细多线程向量微处理器中的操作数多路复用器控制修改器指令
公开(公告)号：US20080122854A1
公开(公告)日：2008-05-29
申请号：US11564072
申请日：2006-11-28
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于处理图像的指令集。矢量处理可以包括在执行向量操作之前在一个或多个源寄存器中重新排列向量操作数。通常，通过发出需要临时寄存器过度使用的多个置换指令来完成源寄存器中操作数的重新排列。此外，置换指令可能导致在流水线中执行的指令之间的相关性，从而不利地影响性能。本发明的实施例提供了一种在寄存器文件和向量单元之间的复用水平，其允许在将操作数提供给向量单元之前重新排列源寄存器中的向量操作数，从而避免了对置换指令的需要。

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